Abstract: The present invention provides a method for manufacturing an optical element to be used for an optical system and an optical instrument using the optical system, and a method for manufacturing a device using the optical instrument, wherein the optical element is manufactured by the steps including the steps for processing a high purity silica glass by lithography, and the hydrogen molecule content is adjusted after manufacturing the optical element.

Abstract: The invention enables a layer of metal to be formed on a substrate with few or no voids formed in the layer, with increased throughput and without raising the temperature of the substrate to a level that may damage the substrate. A layer of metal can be formed on a substrate using a cold deposition step followed by a hot deposition step. The cold deposition step need only be performed for a time sufficient to deposit metal over the entire surface on which the metal layer is to be formed. In the hot deposition step, further metal is deposited while the substrate is rapidly heated to a target temperature. The rapid heating quickly mobilizes the atoms of the deposited metal, making the deposited metal far less susceptible to cusping and voiding than has been the case with previous methods for depositing a metal layer on a substrate that include a cold deposition step followed by a hot deposition step.

Abstract: A lower electrode of a capacitor which has uneven surface formed by using HSG-Si (hemispherical grained silicon) and which is used, for example, in a semiconductor device such as DRAM device. Such lower electrode is fabricated as follows. An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. Then, the silicon film is selectively patterned to pattern it. The semiconductor substrate is heated to remove moisture in the insulating film. An oxide film on the surface of the silicon film is then removed. Thereafter, silicon nuclei are formed on the surface of the silicon film by heating the semiconductor substrate in atmosphere containing silicon compound gas. The silicon nuclei are then grown and thereby a lower electrode is formed which has hemispherical grains on the surface thereof.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film has features that it exhibits {111} orientation and that almost all crystal lattices have continuity at a crystal boundary. This type of grain boundaries greatly contribute to improving the carrier mobility, and make it possible to realize, semiconductor devices having very high performance.

Abstract: A semiconductor memory device comprising: a first insulating film covering the upper and side surfaces of a gate electrode; a second insulating film formed on the substrate covering the first insulating film; a pair of contact holes formed through the second insulating film and reaching the impurity diffusion regions; a conductive plug embedded in one of the contact holes; a third insulating film formed on the second insulating film covering the conductive plug, and having a first aperture on the other contact hole; a bit line formed on the third insulating film and connected to the other impurity diffusion region through the first aperture and the other contact hole; a fourth insulating film covering the upper and side surfaces of the bit line; a second aperture formed through the third insulating film in alignment with the fourth insulating film covering the side surface of the bit line; a storage electrode formed to extend over the bit line, insulated from the bit line by the third and fourth insulating fi

Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.

Abstract: The present invention provides an electrostatic discharge-protection device located between a pad and a specific voltage point. The electrostatic discharge-protection device has a P-type substrate. Then a first N-type well, a first P-type doped region, and a first N-type doped region, are formed on the P-type substrate, wherein the first P-type doped region and the first N-type doped region are coupled to the specific voltage point, respectively. A second P-type doped region and a second N-type doped region are formed on the first N-type well and are coupled to the pad, respectively. Moreover, a third N-type doped region and a fourth N-type doped region are formed on the P-type substrate. The third N-type doped region is coupled to the pad, and a second N-type well is formed between the third N-type doped region and the fourth N-type doped region.

Abstract: A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.

Abstract: A method is described comprising removing an oxide from a surface and then commencing application of a passivation layer to the surface within 5 seconds of the oxide removal. The surface may be a copper surface which may further comprise a bonding pad surface. Removing the oxide may further comprise applying a solution comprising citric acid or hydrochloric acid. Applying the passivation layer may further comprise applying a solution comprising a member of the azole family where the azole family member may further comprise BTA. The method may also further comprise completely applying the passivation layer 35 seconds after commencing its application.

Abstract: A method of manufacturing a flat display is disclosed. First, a first substrate having a first thickness is provided. The first substrate includes a first display area and a first pad area, and a pad electrode is formed in the first pad area and a passivation layer is formed on the pad electrode. Next, a second substrate having a second thickness is provided. The second substrate includes a second display area and a second pad area, the second display area is opposite to the first display area, and the second pad area is opposite to the first pad area. The first substrate and the second substrate are then sealed by a sealing material. After removing the second pad area of the second substrate, the passivation layer on the first pad area is then removed to expose the pad electrode. At the same time, the thickness of the first substrate is reduced from the first thickness to the third thickness.

Abstract: A single tier cavity down integrated circuit package having a die with outer bond pads and staggered inner bond pads is described. The bond pads of the die are assigned to associated supply rings and bond fingers of the package according to a design methodology where in one embodiment at least all bond pads connected to the supply rings are outer bond pads, and staggered inner bond pads are connected to bond fingers. There is further described a method for assigning bond pads of the die to associated supply rings and bond fingers of the package, as well as, a die having staggered bond pads formed in accordance with the method of the present invention.

Abstract: The present invention provides a memory array fabricated by complementary metal-oxide-semiconductor salicide process. The memory array comprises a semiconductor substrate. Multitudes of first isolation devices are aligned in the semiconductor substrate and second isolation devices aligned on the semiconductor substrate. The alignment of the second isolation devices is parallel to one of the first isolation devices. Some polysilicon lines are on the second isolation devices therefor have null memory function. A conductive structure is below a surface of the semiconductor substrate. The conductive structure is located between the first isolation devices. A conductive contact is on the conductive structure. The correspondence of the first isolation devices and the polysilicon lines can prevent the conductive structures from short effect.

Abstract: A photoresist is provided with an opening as a dummy pattern in a space area, i.e., a dummy region, other than a pattern of elements and circuits in one chip, thereby increasing the number of openings in the photoresist and performing ion implantation. This reduces the number of ions entering into the photoresist. As a result, the area in which the photoresist hardens due to the entering ions can be reduced, resulting in improved removability of the photoresist. The occurrence of charge-up can also be reduced. With a reduction in the area of regions other than the openings in the photoresist, a location where strong surface tension is generated can hardly be present. This allows the dimensional accuracy of the photoresist to be improved without making the photoresist thin in film thickness.

Abstract: A BGA package and a method for fabricating the package are provided. The package includes a semiconductor die, internal conductors wire bonded to bond pads on the die, external ball contacts attached to ball bonding pads formed on the conductors in a dense grid pattern, and an encapsulating resin encapsulating the die and conductors. The package is fabricated using a lead frame having lead fingers that form the conductors. The die is back bonded to a polymer tape placed across the lead fingers, and then wire bonded to bonding pads on the conductors. In addition, the encapsulating resin is molded to include openings for the ball contacts which are aligned with the ball bonding pads. An alternate embodiment BGA package includes a polymer substrate adhesively bonded to a face of the die. The polymer substrate includes conductors having beam leads aligned with an opening through the polymer substrate. The opening provides access for a bonding tool for bonding bumps on the beam leads to bond pads on the die.

Abstract: An ion implantation method which can accurately control the effective dose amount even in ion implantation at a very low energy. This ion implantation method comprises the steps of carrying out preamorphization ion implantation for a semiconductor substrate in an ion implantation apparatus; then cleaning the surface of semiconductor substrate in a cleaning apparatus so as to eliminate an oxidized film; and thereafter carrying out ion implantation again in the ion implantation apparatus under a low implantation energy so as to form a shallow junction in the semiconductor substrate. As a consequence, the influence of the oxidized film formed by preamorphization ion implantation can be suppressed, whereby the effective dose can be controlled accurately.

Abstract: A method of forming an electrically conductive via with bumps on both sides of a substrate wherein there is provided a substrate having a pair of opposing surfaces and a via extending between the opposing surfaces. A layer of a material capable of forming a seed for receiving thereon a plating material is provided on one of the surfaces extending to the via. The structure is then placed into an electroplating bath, preferably gold-containing, to electroplate the walls of the via. The electroplated material is then heated to a temperature above its flow or melting temperature in a reducing atmosphere for a time sufficient to cause the electroplated material to fill the via and any voids within the via. The step of heating the electroplated material is preferably to a temperature at least 10 degrees C. above its flow or melting temperature of the electroplated material. The reducing atmosphere is from about 5 percent to 100 percent hydrogen and the remainder preferably nitrogen.

Abstract: A method of manufacturing a semiconductor device comprising the step of epitaxially growing of an n-type doped layer of a semiconductor material using an n-type dopant gas, the growth process being performed at a pressure higher than 2.66×104 Pa.

Abstract: A method of removing a photoresist layer on a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. A dry stripping process is performed to remove the photoresist layer on the semiconductor wafer. The semiconductor wafer is then placed on a rotator of a wet clean chamber and horizontally rotated. A first cleaning process is performed to remove polymers and organic components on a surface of the semiconductor wafer. Then a second cleaning process is performed as well to remove polymers and particles on the surface of the semiconductor wafer. By performing a third cleaning process, a first cleaning solution employed in the first cleaning process and a second cleaning solution employed in the second cleaning process are removed from the surface of the semiconductor wafer. Finally, the semiconductor wafer is spun dry at the end of the method.

Abstract: A tungsten layer formation method for a semiconductor device reduces resistivity of the tungsten layer without requiring modification of the conventional manufacturing system. The method includes treating the surface of a barrier metal layer formed over a semiconductor substrate in a pressure environment of over 40 Torr using SiH4 gas; forming a tungsten seed layer on the treated barrier metal layer using WF6 and SiH4 gases, a mixing ratio {WF6}/{SiH4} of the gases being less than or equal to one; and forming a tungsten layer on the treated barrier metal layer using WF6 gas, the treated barrier metal layer having the tungsten seed layer formed thereon.

Abstract: A semiconductor chip assembly includes a semiconductor chip, a conductive trace, a connection joint, an insulative adhesive and an encapsulant. The conductive trace includes a routing line and a pillar. The routing line extends within and outside a periphery of the chip, and the pillar is disposed outside the periphery of the chip and extends away from the chip. The connection joint contacts and electrically connects the routing line and the pad. The adhesive is sandwiched between the routing line and the chip and contacts a surface of the routing line that faces away from the chip, thereby interlocking the routing line to the assembly. The encapsulant extends into a channel in the pillar, thereby interlocking the pillar to the assembly.