Abstract: Disclosed are layered groupings and methods for constructing digital circuitry, such as memory known as Permanent Inexpensive Rugged Memory (PIRM) cross point arrays which can be produced on flexible substrates by patterning and curing through the use of a transparent embossing tool.

Abstract: A wafer structure is deposited on a composite substrate structure having at least two substrate layers bonded together. A first substrate layer is made of a first substrate material having a first-substrate-layer material transverse coefficient of thermal expansion, greater than the wafer transverse coefficient of thermal expansion, and a second substrate layer is made of a second substrate material having a second-substrate-layer material transverse coefficient of thermal expansion, measured parallel to the transverse direction, less than the wafer transverse coefficient of thermal expansion. The substrate layers are present in relative proportions such that the substrate transverse coefficient of thermal expansion differs from the wafer transverse coefficient of thermal expansion by not more than about 2×10?6/° F.

Abstract: A chalcogenide material is formed to a first thickness over the first conductive electrode material. The chalcogenide material includes AxBy. A layer that includes a metal is formed to a second thickness over the chalcogenide material. The metal including layer defines some metal including layer transition thickness for the first thickness of the chalcogenide material such that when said transition thickness is met or exceeded, said metal including layer when diffused within said chalcogenide material transforms said chalcogenide material from an amorphous state to a crystalline state. The second thickness being less than but not within 10% of said transition thickness. The metal including layer is irradiated effective to break a chalcogenide bond of the chalcogenide material and diffuse at least some of the metal into the chalcogenide material.

Abstract: Films of gallium manganese nitride are grown on a substrate by molecular beam epitaxy using solid source gallium and manganese and a nitrogen plasma. Hydrogen added to the plasma provides improved uniformity to the film which may be useful in spin-based electronics.

Abstract: A method to form transistors having improved ESD performance in the manufacture of an integrated circuit device is achieved. The method includes providing a SOI substrate with a doped silicon layer and a buried oxide layer. The doped silicon layer has a first conductivity type and overlies the buried oxide layer. Ions are implanted into the SOI substrate to form higher concentration regions in the doped silicon layer. The higher concentration regions have the first conductivity type and are formed substantially below the top surface of the doped silicon layer. MOS gates are formed. These MOS gates include an electrode layer overlying the doped silicon layer with a gate oxide layer therebetween. Source and drain regions are formed in the doped silicon layer to complete the transistors in the manufacture of the integrated circuit device. The source and drain regions contact the higher concentration regions and have a second conductivity type.

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A method of fabricating and mounting a flip chip includes using an environmentally friendly plasma gas, which minimizes safety hazards during an implementation of the method and does not require an additional heat source during a reflow process thereof. That is, the method includes reflowing a solder bump using an argon-hydrogen plasma process. The argon-hydrogen plasma process used to fabricate the flip chip includes maintaining a pressure in a chamber at 250 to 270 mtorr, feeding a mixed gas of argon with 10 to 20% hydrogen to the chamber to generate a plasma with power of 100 to 200 W, and exposing the flip chip to the plasma for 30 to 120 seconds. Additionally, an argon-hydrogen plasma process used to mount the flip chip includes maintaining pressure in a chamber at 100 to 400 mtorr, feeding a mixed gas of argon with 0 to 20% hydrogen to the chamber to generate a plasma with power of 10 to 50 W, and exposing the flip chip to the plasma for 10 to 120 seconds.

Abstract: A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to subsequently formed conductive lines of the magnetic memory device. A sacrificial mask is used to pattern the bottom electrode material, and at least a portion of the sacrificial mask is consumed or removed during the patterning of the bottom electrode material. The soft layer is then deposited and patterned using a hard mask.

Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.

Abstract: The present invention provides a method for creating microscopic high resistivity structures on a target by directing a focused ion beam toward an impact point on the target and directing a precursor gas toward the impact point, the ion beam causing the precursor gas to decompose and thereby deposit a structure exhibiting high resistivity onto the target. The precursor gas preferably contains a first compound that would form a conductive layer and a second compound that would form an insulating layer if each of the first and second compounds were applied alone in the presence of the ion beam.

Abstract: The invention includes a semiconductor processing method wherein an insulative mass is formed across a first electrical node and a second electrical node. The mass has a pair of openings extending therethrough to the electrical nodes. The individual openings each have a periphery defined by one of the electrical nodes and at least one sidewall. One of the openings extends to the first electrical node and is a first opening, and the other of the openings extends to the second electrical node and is a second opening. A dielectric material layer is formed within the openings to narrow the openings. Conductive material plugs are formed within the narrowed openings. The conductive material plug within the first opening is a first material plug, and is separated from the first electrical node by the dielectric material; and the conductive plug within the second opening is a second material plug, and is not separated from the second electrical node by the dielectric material.

Abstract: A semiconductor device and a method of making a semiconductor device. A damascene metal layer (16) is formed in an insulating dielectric layer (12), which is in direct electrical communication with a substrate (10). A layer of a passive element, such as first capacitor electrode layer (20) is disposed on metal layer (16) and preferably is offset relative to metal layer (16) to allow a direct electrical interconnect through a via (36) to metal layer (16). In one embodiment a capacitor and a resistor are formed as passive elements in the device. In another embodiment, the passive element includes at least one resistor (28) and optionally a second resistor (32). In yet another embodiment, metal layer (16) is a damascene copper layer.

Abstract: A monolithic semiconductor optical device with excellent temperature and modulation characteristics and associated method of manufacturing whereby the device has a semiconductor substrate, a semi-insulating buried heterostructure GaInAsP-based DFB laser; and either a buried ridge type AlGaInAs-based EA or a self aligned structure (SAS) AlGaInAs-based EA modulator.

Abstract: The capacitance of deep trench capacitors is enhanced by increasing the surface area of the doped region of the trench to be used for one electrode of the capacitor. After formation of the deep trench and a collar on an upper region of the trench, and after optional bottling of the trench, hemispherical silicon grain (HSG) is deposited on a lower region of the trench. The HSG is then oxidized, along with that portion of the silicon substrate not covered by HSG, to form a roughened surface in the trench, thereby enhancing the trench capacitance. Oxidation of the HSG and the substrate occurs simultaneously with formation of the buried plate, and the formed oxide may be stripped along with the collar, thereby providing a simpler and more robust capacitance enhancement scheme.

Abstract: A support assembly for mounting a semiconductor device vertically relative to a carrier substrate. The support assembly includes an interposer to which the semiconductor device is attached. The support assembly also includes traces carried on the interposer, which electronically connect the semiconductor device to contacts on the interposer. The contacts are disposed along a single edge of the interposer. The invention also includes an alignment device for releasably mounting the support assembly. The alignment device, which mounts to a carrier substrate, includes one or more receptacles. As a support assembly is inserted into a receptacle, the alignment device establishes an electrical connection between the contacts and corresponding terminals on the carrier substrate. The assembly may also include a cover that attaches to the top of the alignment device and biases the interposer against the carrier substrate.

Abstract: The present invention relates particularly to a method of and an apparatus for forming a fine interconnection in a highly integrated circuit formed on a semiconductor substrate. The method has the steps of preparing a substrate having fine recesses formed in a surface thereof, dispersing ultrafine particles made at least partly of a metal in a predetermined solvent, producing an ultrafine particle dispersed liquid, supplying the ultrafine particle dispersed liquid to the fine recesses of the substrate, heating the substrate to melt and bond the metal, and chemical mechanical polishing the surface of the substrate to remove an excessively attached metal therefrom. According to the present invention, it is possible to stably deposit an interconnection metal of good quality using an inexpensive material.

Abstract: A planarization method includes providing an aluminum-containing surface and positioning it for contact with a fixed abrasive article in the presence of a composition preferably including a surfactant, a complexant, and an oxidant, wherein the solution has a pH of less than about 10.

Abstract: A system for processing residual gas that includes a chamber having at least one baffle for increasing gas flow path, a residual gas inlet mechanism connected to the chamber for supplying residual gas to the chamber, at least one first gas inlet mechanism connected to the chamber for supplying inert gas to the chamber, at least one second gas inlet mechanism connected to the chamber for supplying a reactive gas to the chamber, and a gas outlet mechanism for connected to the chamber for outputting mixed gases from mixing the residual gas, inert gas and reactive gas and non-reacted residual gas, inert gas and reactive gas.

Abstract: Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film. Additionally, methods and apparatuses are disclosed that can introduce deliberate semiconductor film variations to determine optimal device characteristics or produce small production runs. Introducing semiconductor film variations, such as thickness variations and/or composition variations, allow different devices to be made. A number of devices may be made having variations in semiconductor film.

Abstract: A method for forming a semiconductor device includes providing a lead frame which has a die pad and a plurality of leads extending toward the outside of the die pad, mounting a semiconductor chip on the die pad, defining a plurality of inner leads by cutting a predetermined cut portion on each of the leads located around the semiconductor chip, and bonding a wire between the inner leads and the semiconductor chip. Accordingly, an applicable lead frame is provided for several sizes of a semiconductor chip.