Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C.

Abstract: A semiconductor device manufacturing method having a multi-layered wiring structure comprises the steps of forming an insulating film over a semiconductor substrate, coating resist on the insulating film, forming a wiring pattern window in the resist, forming a wiring recess by etching the insulating film via the window, removing the resist, removing a reaction product existing on the insulating film by exposing the insulating film to a plasma atmosphere using an inactive gas, and burying a metal film into the wiring recess to form a wiring.

Abstract: The present invention provides a coating film, which is not likely to cause cracks on the coated surface and is also capable of improving the resistance of the coated surface, especially oxidation resistance, corrosion resistance, and gas permeation resistance, a member provided with the coating film, and a method for producing the coating film. In the coating film of the present invention, a dense layer containing silicon dioxide as a principal component, which is obtained by heat-treating a solution containing perhydropolysilazane and polyorganosilazane, a ratio of the content of perhydropolysilazane to the total amount of polysilazane including perhydropolysilazane and polyorganosilazane being from 0.65 to 0.95, in air or air containing water vapor, was formed on the surface of a stainless steel plate.

Abstract: First, a trench of a semiconductor substrate is filled with a polysilicon film deposited on the surface of the semiconductor substrate. A selective thin film having etching selectivity with respect to the polysilicon film is formed on the polysilicon film. Then, the selective thin film is etched (etched back) so that a part of the selective thin film remains in a depression of the polysilicon film, as a self-aligning mask. The polysilicon film is further etched with the self-aligning mask, thereby forming a polysilicon embedded layer in the trench with a flat surface.

Abstract: A MOSFET includes: a first conductivity type a semiconductor substrate having a trench formed in a surface area thereof, a gate electrode formed on the semiconductor substrate; and a trench gate electrode which is adjacent to the gate electrode and is buried in the trench, and which generates an output by AND logic in response to inputs to the gate electrode and the trench gate electrode, wherein an impurity concentration directly below the gate electrode is higher than an impurity concentration directly below the trench gate electrode.

Abstract: The invention pertains to a method of making a photovoltaic cell at least comprising the following layers in the following order: a first electrode layer, a transparent wide band gap semiconductor layer provided with a layer of a photosensitising dye or pigment which in combination with the semiconductor layer has the ability to spatially separate photogenerated electrons from their positive countercharges, a layer of an electrolyte, a catalyst layer, and a second electrode layer. The method is characterized in that the first electrode layer and the semiconductor layer and/or the second electrode layer and the catalyst layer are deposited on a flexible temporary substrate that is removed later on. The electrode or electrodes, which are deposited on the temporary substrate, are transparent. The invention allows the roll-to-roll manufacture of said photovoltaic cell while providing great freedom in selecting the processing conditions.

Abstract: Described is a method of fabricating an organic electroluminescent display (hereinafter abbreviated OELD) enabling to increase a throughput efficiency by carrying out a foregoing OELD process, dividing a large-scaled substrate, and carrying out a following OELD process in order. The present invention includes the steps of forming a first electrode layer on a large-scaled substrate, dividing the large-scaled substrate into a plurality of small substrates, forming an organic electroluminescent layer on the first electrode layer of at least one of the small substrates, and forming a second electrode layer on the organic electroluminescent layer.

Abstract: A method for making a silicon substrate having a buried thin silicon oxide film is described. The method consists of: a) producing a first element having a first silicon body whereof the main surface is coated, in succession, with a buffer layer of germanium, or of an alloy of germanium and silicon, and with a thin silicon film; b) producing a second element, having a silicon body whereof a main surface is coated with a thin silicon oxide film; c) linking the first element with the second element such that the thin silicon film of the first element is in contact with the thin silicon oxide film of the second element; and d) eliminating the buffer layer to recuperate the silicon substrate having a buried thin silicon oxide film and a reusable silicon substrate. The method may be useful in making microelectronic devices such as CMOS and MOSFET devices.

Abstract: A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.

Abstract: To provide a method for producing a non-volatile semiconductor memory device that can form trenches having different depths in a reduced number of processes.

Abstract: A zener diode is formed in a bipolar or BiCMOS fabrication process by modifying the existing masks that are used in the bipolar or BiCMOS fabrication process, thereby eliminating the need for a separate doping step. In addition, the reverse breakdown voltage of the zener diode is set to a desired value within a range of values by modifying the area of a new opening in one of existing masks.

Abstract: A method of forming a trench isolation structure prevents a nitride liner from being over-etched, i.e., prevents the so-called dent phenomenon from occurring. An etching mask pattern is formed on a semiconductor substrate. A trench is formed in the substrate by using the etching mask pattern as an etching mask. A nitride liner, serving as an oxidation barrier layer, is formed at the sides and bottom of the trench, and is then annealed in a furnace to density the same. In a subsequent etching process, such as that used to remove the etching mask pattern, the densified nitride liner resists being etched. Accordingly, a trench isolation structure having a good profile is produced.

Abstract: A method of manufacturing a semiconductor device that eliminates the n+ contact implant by using double diffused implants under the core cell contacts by forming core, n-channel and p-channel transistors in a semiconductor substrate, simultaneously forming source and drain DDI implants for the core transistors, forming source and drain Mdd implants for the core transistors, forming source and drain Pldd implants for the p-channel transistors, forming source and drain Nldd implants for the n-channel transistors, forming sidewall spacers on the core, n-channel and p-channel transistors, forming N+ implants for the n-channel transistors, forming P+ implants for the p-channel transistors and forming P+ contact implants for the p-channel transistors.

Abstract: A semiconductor dry etching process that provides deep, smooth (RMS of less than approximately 5 nm), and vertical etching of InP-based materials with ICP RIE using a chlorinated plasma with the addition of hydrogen gas. Inert gases such as nitrogen, argon, or both may also be included. To produce relatively high anisotropy with exceptionally smooth surfaces, the amount of hydrogen gas added preferably exceeds the volumetric measure of chlorinated gas in standard cubic centimeter per minute (sccm); at a ratio of greater than 1:1. The present invention provides an improved dry etching process for InP-based semiconductor materials that yields deep, vertical etch profiles with improved surface smoothness (i.e., morphology) and high manufacturing etch rates.

Abstract: A method of manufacturing a TFT (10) is disclosed comprising source (8) and drain (8″) electrodes joined by a semiconductor channel (6) formed from a semiconductor layer (4), a gate insulating layer (7) and a gate electrode (8′). The method comprising the steps of applying a foil (2) comprising a crystallization enhancing material (CEM) and depositing the semiconductor layer (4) over a supporting substrate (1); and heating the semiconductor layer (4) so as to crystallize the semiconductor layer (4) from regions exposed to the CEM of the foil (2). The method may further comprise the step of providing a patterned barrier layer (3) between the foil (2) and the semiconductor layer (4) wherein the semiconductor layer (4) is crystallized from regions exposed through vias in the barrier layer (3) to the CEM of the foil (2).

Abstract: The present invention provide a vertical nano-sized transistor using carbon nanotubes capable of achieving high-density integration, that is, tera-bit scale integration, and a manufacturing method thereof, wherein in the vertical nano-sized transistor using carbon nanotubes, holes having diameters of several nanometers are formed in an insulating layer and are spaced at intervals of several nanometers. Carbon nanotubes are vertically aligned in the nano-sized holes by chemical vapor deposition, electrophoresis or mechanical compression to be used as channels. A gate is formed in the vicinity of the carbon nanotubes using an ordinary semiconductor manufacturing method, and then a source and a drain are formed at lower and upper parts of each of the carbon nanotubes thereby fabricating the vertical nano-sized transistor having an electrically switching characteristic.

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base, a conductive trace and a through-hole between its top and bottom surfaces. The through-hole includes a top sidewall portion adjacent to the top surface and a bottom sidewall portion adjacent to the bottom surface. The conductive trace includes a pillar at the top surface and a routing line at the bottom sidewall portion. An electrolessly plated contact terminal on the pillar extends above the base, and an electrolessly plated connection joint in the through-hole connects the routing line and the pad. Preferably, the connection joint is the only metal in the through-hole. A method of manufacturing the assembly includes simultaneously electrolessly plating the contact terminal and the connection joint.

Abstract: A semiconductor chip assembly includes a semiconductor chip attached to a support circuit. The support circuit includes an insulative base and a conductive trace. The conductive trace includes a pillar and a routing line. An electroplated contact terminal contacts the pillar, and an electroplated connection joint contacts the routing line and the pad. A method of manufacturing the assembly includes simultaneously electroplating the contact terminal and the connection joint.

Abstract: A semiconductor device having an alternating conductivity type layer improves the tradeoff between the on-resistance and the breakdown voltage and facilitates increasing the current capacity by reducing the on-resistance while maintaining a high breakdown voltage. The semiconductor device includes a semiconductive substrate region, through which a current flows in the ON-state of the device and that is depleted in the OFF-state. The semiconductive substrate region includes a plurality of vertical alignments of n-type buried regions 32 and a plurality of vertical alignments of p-type buried regions. The vertically aligned n-type buried regions and the vertically aligned p-type buried regions are alternately arranged horizontally. The n-type buried regions and p-type buried regions are formed by diffusing respective impurities into highly resistive n-type layers 32a laminated one by one epitaxially.

Abstract: A ruthenium containing metal 6′ adhering to a periphery of a device forming area, an end face and a rear face in a silicon substrate 10 is removed using a first remover containing (a) at least one compound selected from the group consisting of salts containing chlorate, perchlorate, iodate, periodate, salts containing bromine oxide ion, salts containing manganese oxide ion and salts containing tetravalent cerium ion and (b) at least one acid selected from the group consisting of nitric acid, acetic acid, iodic acid and chloric acid. After the removing treatment, the substrate is washed with hydrofluoric acid to remove the residual remover.