Abstract: A method of and an apparatus for manufacturing semiconductors, in which a liquid raw material can be uniformly supplied onto a wafer and a gas required for film formation can be also uniformly supplied onto the wafer. A liquid raw material is sprayed from a tip end of a vaporizing nozzle into a vacuum chamber as liquid droplets, and is vaporized by heat generated from the wafer placed on a susceptor. When the liquid raw material is sprayed, a gas required for film forming reaction is supplied into the vacuum chamber from a gas supply pipe provided on an outer periphery of the vaporizing nozzle. The vaporizing nozzle and the gas supply pipe are formed to be concentric, and a liquid raw material spray port is formed centrally of the vaporizing nozzle.

Abstract: A method of fabricating a memory device. A plurality of isolation structures and a plurality of stacked gate structures are sequentially formed on a substrate. While defining the stacked gate structures, the isolation structures are over etched to form a plurality of trenches. A material layer is filled into the trenches. A patterned photoresist layer is formed on the substrate, while a part of the substrate predetermined for forming a drain region is exposed. An ion implantation step is performed to implant a dopant into the part of substrate predetermined for forming the drain region, such that a well is formed. As the trenches are filled with the material layer, the dopant cannot penetrate therethrough.

Abstract: The reliability and electromigration resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer with at least one alloying element for the metal of the feature, and then uniformly diffusing at least a minimum amount of the at least one alloying element of the at least one thin layer for a predetermined minimum depth below the upper surface of the features to effect alloying therewith. The alloyed portions of the metallization features advantageously reduce electromigration therefrom. Planarization, as by CMP, may be performed subsequent to diffusion/alloying to remove any remaining elevated, alloyed or unalloyed portions of the at least one thin layer.

Abstract: A method of manufacturing a semiconductor device is provided. The method including the steps of forming an insulating interlayer film on a substrate, forming a Cu interconnection pattern in the insulating interlayer film, forming a first insulating film on the insulating interlayer film at a first temperature lower than 400° C. in a nonoxide situation so that the first insulating film covers the Cu interconnection pattern, and forming a second insulating film on the first insulating film at a second temperature higher than the first temperature.

Abstract: A method and apparatus for reducing gouging during via formation. In one embodiment, the present invention is comprised of a method which includes forming an opening into a substrate. The opening is formed extending into the substrate and terminating on at least a portion of a target to which it is desired to form an electrical connection. After the formation of the opening, the present embodiment lines the opening with a liner material. In this embodiment, the liner material is adapted to at least partially fill a portion of the opening which is not landed on the target. The liner material of the present embodiment prevents substantial further etching of the substrate conventionally caused by the opening being at least partially unlanded on the target. Next, the present embodiment subjects the liner material to an etching process such that the liner material is substantially removed from that region of the target where the opening was landed on the target.

Abstract: A method of manufacturing a MOSFET semiconductor device includes forming a gate electrode over a substrate and a gate oxide between the gate electrode and the substrate. Inert dopants are then implanted within the substrate to form amorphized source/drain regions in the substrate extending to a first depth significantly greater than the intended junction depth. The amorphized source/drain regions are implanted with source/drain dopants such that the dopants extend into the substrate to a second depth less than the first depth, above and spaced apart from the end-of-range defect region created at the first depth by the amorphization process. Laser thermal annealing recrystallizes the amorphous regions, activates the source/drain regions and forms source/drain junctions.

Abstract: Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.

Abstract: An integrated circuit includes first and second diodes that are electrically connected to a conductive line in antiparallel, to dissipate both positive and negative charges on the conductive line during plasma processing. The integrated circuit also includes a fuse for disconnecting one of the first and second diodes from the conductive line after the plasma processing, to thereby allow conduction of one of positive and negative charge on the conductive line after the plasma processing. Accordingly, integrated circuits are fabricated by forming a conductive line on an integrated circuit substrate and first and second diodes in the integrated circuit substrate that are electrically connected to the conductive line in antiparallel. Then, plasma processing is performed on the integrated circuit substrate including the conductive line and the first and second diodes, such that the first and second diodes dissipate both positive and negative charges on the conductive line during the plasma processing.

Abstract: Excessive variation in vertical (i.e., inter-level) capacitance of multi-level metallization semiconductor devices resulting in racing of clock skew circuitry of finished devices, and over-etching of borderless vias leading to inter-level short-circuits, are simultaneously eliminated, or substantially reduced, by selectively providing an etch-resistant masking material at thinner, i.e., recessed, portions of a first, low k gap fill material blanket-deposited over spaced-apart features of a metallization pattern and in the spaces therebetween. The surfaces of thicker, non-recessed portions thereof are etched so as to be substantially co-planar with the feature surfaces and the recessed portions. The etch-resistant mask is then removed, and second, oxide-based and third, low k dielectric layers deposited over the planarized surface.

Abstract: A process of forming a nitride film on a semiconductor substrate including exposing a surface of the substrate to a rapid thermal process to form the nitride film.

Abstract: A method for fabricating LGA-, LCCY- and BGA-types of very thin, chip size semi-conductor packages (“VCSP's”) includes substantially reducing the thickness of a semiconductor wafer containing the semiconductor chips to be packaged by grinding and/or etching the wafer from its back side prior to singulation of the chips from the wafer. The thinned-down chips thus produced are electrically connected to corresponding insulative substrates contained in an integral array thereof using the “flip chip” interconnection method. The narrow row space between the chips and the substrates are sealed with an underfill material, and the individual, finished VCSP's are then singulated from the array.

Abstract: A semiconductor device includes: a support member (20) on which a land (24) is formed; a semiconductor chip (10) having a bump for an electrode (12) that is disposed on the land (24), and to be bonded face-down to a support member (20); and resin (30) which is provided as an adhesive between the semiconductor chip (10) and the support member (20), which is allowed to contract on hardening, and which causes pressure-bonding between the land (24) and the bump (12) by the stress due to this hardening contraction. The stress therein is partially absorbed by elastic deformation of at least the support member (20).

Abstract: An interconnection structure preferably including one or more conductors that have a central region filled with an insulator, and a method of fabricating such an interconnection structure for preferably making an electrical connection to the conductor(s). The method preferably includes the steps of depositing and patterning a first insulator over a substrate to form an aperture opening to the substrate; depositing and polishing a first conductor to leave the first conductor in the aperture; depositing and patterning a second insulator to form an opening through the second insulator and a recess in the aperture; depositing one or more second conductors to line the opening and the recess, and to form a central region of the interconnection structure; depositing a third insulator to at least partially fill the central region; and making an electrical connection to the second conductor(s).

Abstract: A semiconductor device having laminated successively a porous semiconductor layer, an inorganic semiconductor layer, and optionally an organic substance layer formed therebetween is disclosed. The semiconductor device is produced by immersing a porous semiconductor layer or a semiconductor layer having an organic substance layer on the surface thereof in a solution containing the elements constituting an inorganic semiconductor or compounds of the elements and forming the inorganic semiconductor layer on the porous semiconductor layer or the organic substance layer in the solution.

Abstract: The present invention is related to a method of manufacturing high efficiency LEDs. The LEDs uses a metal reflection layer to solve the problem of light absorption by the substrate, and improves the illumination. It also forms a vertical structure where the P and N ends are on the top and bottom sides of the LEDs, respectively. A vertical structure is easier for final packaging. In addition, the present invention uses a metal substrate to replace the semiconductor substrate in order to improve the heat dissipation, and enable the LEDs to operate at a higher current.

Abstract: The method disclosed herein provides a semiconducting substrate, positioning the substrate in a high density plasma process chamber, and forming a layer of silicon-rich silicon dioxide above the substrate using a high density plasma process with an oxygen/silane flowrate ratio that is less than or equal to 0.625. In another embodiment, the method provides a semiconducting substrate having a partially formed integrated circuit device formed thereabove, the integrated circuit device having a plurality of conductive interconnections, e.g., conductive lines or conductive plugs, formed thereon, and positioning the substrate in a high density plasma process chamber. The method further includes forming a first layer of silicon dioxide between the plurality of conductive interconnections using a high density plasma process with an oxygen/silane flowrate ratio less than 1.0, and forming a layer of insulating material above the first layer between the conductive interconnections.

Abstract: A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH3) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0×1015 atoms/cm2 to about 6.0×1015 atoms/cm2, and has a thickness which may be controlled within a sub 10 Å range.

Abstract: A process for heat treating a silicon wafer to dissolve B-type agglomerated interstitial defects present therein. The process includes heating the silicon wafer at a temperature for a time sufficient to dissolve B-defects, the wafer being heated to said temperature at a rate sufficient to prevent B-defects from becoming stabilized such that these defects are rendered incapable of being dissolved.

Abstract: The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. The same material may also be used as a barrier layer and an etch stop, even in complex damascene structures and with high diffusion conductors such as copper as a conductive material. Under certain process parameters, a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers. The thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to obtain a given reflectivity.

Abstract: A method of manufacturing a trench structure for a trench MOSFET, including the steps of providing a semiconductor substrate having a major surface, forming a dielectric pillar on the substrate major surface (the dielectric pillar extending substantially perpendicularly from the major surface of the substrate), selectively forming a semiconductor layer around the dielectric pillar, and removing a predetermined length of the dielectric pillar to create a trench in the substrate, the trench defined by sidewalls and a bottom. The method permits the controlled formation of a dielectric plug at the bottom of the trench, the plug having predetermined dimensions.