Patents Examined by Richard B. Franklin
  • Patent number: 10372639
    Abstract: An information handling system includes an Inter-Integrated Circuit (I2C) master device and an I2C slave device coupled to the I2C master device via an I2C bus. The I2C slave device is configured with a pre-set I2C address and includes seeding data that is unique to the I2C slave device. The I2C master device receives the seeding data and addresses the I2C slave device at an I2C slave address instead of at the pre-set I2C address, wherein the I2C slave address is based upon the seeding data.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: August 6, 2019
    Assignee: Dell Products, LP
    Inventors: Karthik Venkatasubba, Elie A. Jreij
  • Patent number: 10366019
    Abstract: A multiprocessor system includes several processors, a Shared Local Memory (SLMEM) that stores instructions and data, a system interface block, a posted transaction interface block, and an atomics block. Each processor is coupled to the system interface block via its AHB-S bus. The posted transaction interface block and the atomics block are shared resources that a processor can use via the same system interface block. A processor causes the atomics block to perform an atomic metering operation by doing an AHB-S write to a particular address in shared address space. The system interface block translates information from the AHB-S write into an atomics command, which in turn is converted into pipeline opcodes that cause a pipeline within the atomics block to perform the operation. An atomics response communicates result information which is stored into the system interface block. The processor reads the result information by reading from the same address.
    Type: Grant
    Filed: September 4, 2016
    Date of Patent: July 30, 2019
    Assignee: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Patent number: 10346341
    Abstract: Examples disclosed herein provide for the detection of an orientation of a device docked to a docking station for the device. Based on the orientation, the device may route logic on the device so that connection points on the device to make contact with connection points on the docking station are properly mapped to input/output ports on the docking station.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: July 9, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robin T Castell, Richard E Hodges, Scott P Saunders
  • Patent number: 10339076
    Abstract: A method performed by an information handling system, the method including detecting that a first device has been connected to the information handling system (IHS). The method further including in response to detecting that the first device has been connected, updating one or more fabric consistency validation rules of the IHS associated with the first device and one or more other devices that are connected to the first device by one or more links, and validating that the first device is compatible with each of the other devices based on the updated fabric consistency validation rules of the IHS.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 2, 2019
    Assignee: Dell Products, LP
    Inventors: Binay A. Kuruvila, Sudhir Shetty
  • Patent number: 10338664
    Abstract: A control module used with a peripheral unit having configuration information through a system bus includes a storage unit, a state machine unit and an event detector. The storage unit is configured to store a program. The state machine unit is configured to operate under the program. The event detector is configured to receive a hardware interrupt signal from the peripheral unit via an additional wire, wherein the event detector triggers the state machine to perform one of storing and retrieving the configuration information respectively to and from the storage unit via the system bus.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: July 2, 2019
    Assignee: M2 COMMUNICATION INC.
    Inventors: Fabien Petitgrand, Huang-Lun Lin
  • Patent number: 10331603
    Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: June 25, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Cameron Buschardt, James Leroy Deming, Brian Fahs, Mark Hairgrove, John Mashey
  • Patent number: 10324884
    Abstract: Technology is provided for a memory drive adapter. The memory drive adapter is used for combining memory drives within an alternative form factor. For example the memory drive adapter can include an adapter frame configured for compatibility with a peripheral component interface. The adapter frame can include first and second spaced apart cover panels. A mounting panel extends between the first and second cover panels. An end panel is positioned opposite the mounting panel and extends between the first and second cover panels. One or more divider tabs extend between the first and second cover panels substantially midway between the mounting panel and the end panel to define a pair of drive bays, each configured to receive a 2.5-inch solid state drive.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 18, 2019
    Assignee: Facebook, Inc.
    Inventor: Jon Brian Ehlen
  • Patent number: 10318174
    Abstract: A computer system includes a host and a storage device. The host provides an input/output request (IO request). The storage device receives the request from the host and sends an interrupt informing input/output completion (IO completion) to the host after completing the IO request. The host adjusts the number of generated interrupts of the storage device using the number of delayed IOs. The computer system may adaptively control interrupt generation of the storage device based on a load status of a CPU or the number of delayed IOs. The interrupt generation of the storage device may be adjusted to obtain a CPU gain without loss of performance or processing time of the computer system.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 11, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyung-San Kim, Kyung Ho Kim, Seokhwan Kim, Seunguk Shin, Jihyun Lim
  • Patent number: 10303643
    Abstract: A multi-modulation scheme is provided that combines pulse-width modulation and phase modulation to transmit a plurality of GPIO signals as virtual GPIO signals.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: May 28, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Lalan Jee Mishra, Richard Wietfeldt, Mohit Prasad, James Panian
  • Patent number: 10296216
    Abstract: Executing connections from a data processing system to a storage controller using ports specified in a TPG report. The storage controller receives a RTPG SCSI request from the data processing system via a FC fabric. The storage controller determines whether NPIV is enabled on the storage controller and, if so, the storage controller modifies the TPG report to include one or more dedicated N-Ports and one or more multi-purpose N-Ports, where AAS bits of a dedicated N-Port descriptor associated with the dedicated N-Ports are set as Active/optimized. The storage controller sends the modified TPG report to the data processing system. The storage controller then processes an access request received from the data processing system where the access request is received on one of the one or more dedicated N-Ports and the one or more multi-purpose N-Ports according to the TPG report and a device type of the data processing system.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Christopher W. Bulmer, Timothy A. Moran
  • Patent number: 10289308
    Abstract: A system and method for providing an interconnected data storage system that is able to avoid multiple data transfers, and thus increase the overall performance of the interconnected data storage system. A unified data bus interconnects a computing device with a plurality of storage devices via a plurality of storage systems; each of the plurality of storage systems having a main memory, processor, at least one storage controller, and a connecting port. The unified data bus is a local, high bandwidth bus that allows resources to be shared between the plurality of storage systems and with the computing device. Additionally, the unified data bus allows data to be transferred from the computing device to each of the plurality of storage devices in a single multi-target transfer. Furthermore, the architecture allows for a simpler management software that further increases performance of the interconnected data storage system.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: May 14, 2019
    Inventor: Ricardo Eugenio Velez-McCaskey
  • Patent number: 10289492
    Abstract: A system having a first mode, a second mode and a system bus comprises a peripheral circuit, a power management unit (PMU), an additional wire and a control module. The peripheral circuit has a configuration information representing a circuit state thereof. The power management unit (PMU) generates an interrupt signal. The additional wire transmits therethrough the interrupt signal. The control module, in response to the interrupt signal, stores the configuration information via the system bus when the system is in the first mode and restores the configuration information via the system bus when the system is in the second mode.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: May 14, 2019
    Assignee: M2 Communication Inc.
    Inventors: Fabien Petitgrand, Huang-Lun Lin
  • Patent number: 10282341
    Abstract: Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Bryan L. Spry, Marcus W. Song, Deepak M. Rangaraj, Avinash N. Ananthakrishnan, Robert J. Hayes, Aimee D. Wood, Adam E. Letendre, Brent R. Boswell
  • Patent number: 10268611
    Abstract: A method includes automatically assigning, by at least one processor, an IEC address to an I/O binding variable for an RTU. This includes identifying a type of the I/O binding variable and identifying a size of the I/O binding variable based on the identified type. The size represents a number of memory locations to be used to store the I/O binding variable in at least one memory of the RTU. This also includes, in response to determining that the at least one memory contains a free space to store the I/O binding variable based on the identified size, assigning the IEC address identifying the free space to the I/O binding variable.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: April 23, 2019
    Assignee: Honeywell International Inc.
    Inventors: Li Xiao, Danhua Zhang, Changqiu Wang, Shuang Liang
  • Patent number: 10268614
    Abstract: A method and architecture for operating with distributed (or segmented) on-chip digital interfaces such as the Inter-Integrated Circuit protocol and a Serial Peripheral Interface protocol. This method and architecture, illustratively, divides the available address space of the digital interface register arrays of a device into one or more segments referred to as a fundamental digital interface circuit. Such segmentation allows for each fundamental digital interface circuit to be placed in proximity of the digitally controlled circuit(s) (e.g., analog circuit(s)) which share some operational connection and for exchanging communication in accordance with a plurality of inputs to the device.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: April 23, 2019
    Assignee: NOKIA OF AMERICA CORPORATION
    Inventors: Shahriar Shahramian, Yves Baeyens, Ut-Va Koc
  • Patent number: 10261699
    Abstract: In accordance with embodiments of the present disclosure, a method of transmitting data in an information handling system may include receiving, at a hardware logic device from a host system processor of the information handling system, an input/output (I/O) command; storing the I/O command in a controller memory of the hardware logic device that emulates to the host system processor a controller memory of a memory storage device; communicating a notification of the I/O command to a plurality of memory storage devices communicatively coupled to the hardware logic device; coalescing a plurality of command fetch requests received from individual memory storage devices of the plurality of memory storage devices into a coalesced command fetch request; communicating the coalesced command fetch request to the controller memory; and duplicating a command fetch response from the controller memory of the coalesced command fetch request to the plurality of memory storage devices.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: April 16, 2019
    Assignee: Dell Products L.P.
    Inventors: Srikrishna Ramaswamy, Shyam T. Iyer, Duk M. Kim
  • Patent number: 10255223
    Abstract: Provided are techniques for detecting a type of storage adapter connected to an Input/Output (I/O) bay and miscabling of a microbay housing the storage adapter. Under control of an Input/Ouput (I/O) bay, cable sidebands are driven high for a predetermined period of time. It is determined whether a cable sidebands response has been detected that indicates that the cable sidebands have been driven low. In response to determining that the cable sidebands response has been detected, it is determined that the I/O bay is connected to a first storage adapter supporting a first protocol for the cable sidebands. In response to determining that the cable sidebands response has not been detected, it is determined that the I/O bay is connected to a second storage adapter supporting a second protocol for the cable sidebands. Moreover, I/O bay and port numbers stored by the microbay are used to determine miscabling.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Gary W. Batchelor, Enrique Q. Garcia, Jay T. Kirch, Trung N. Nguyen, Todd C Sorenson
  • Patent number: 10248600
    Abstract: A remote control system includes computing boards and a control board. The control board includes a first network physical layer protocol conversion chip, a network signal switch module and a network signal processing module. The control board is electrically connected to the computing boards and communicated with a remote control manager. The first network physical layer protocol conversion chip is electrically connected to the remote control manager. The network signal switch module is electrically connected to the first network physical layer protocol conversion chip and the computing boards. The network signal processing module is electrically connected to the network signal switch module.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: April 2, 2019
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventor: Lanlan Fang
  • Patent number: 10241954
    Abstract: In some examples, a power delivery system includes a primary power path to provide power to a computing system. The power delivery system also includes a bypass power path. A port manager is to disable the primary power path and to enable the bypass power path in response to a dead battery condition.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Chee Lim Nge, Basavaraj B. Astekar, Jenn Chuan Cheng
  • Patent number: 10223323
    Abstract: First and second apparatuses are connected with each other through a communication path provided with a plurality of lanes used for data transfer that is performed between the first and second apparatuses. Prior to data transfer, transfer-control information is exchanged between the first and second apparatuses according to a predetermined communication protocol. Upon detecting transfer-control information, the first apparatus notifies the second apparatus of a lane-control instruction to increase a second lane-counter indicating a number of lanes used by the second apparatus, and increases a first lane-counter indicating a number of lanes used by the first apparatus so that the first lane-counter is greater than a number of lanes that have been used when detecting the transfer-control information.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 5, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Atsuyuki Nikami, Toshiyuki Shimizu, Tomohiro Inoue