Patents Examined by Richard B. Franklin
  • Patent number: 11449270
    Abstract: The present application provides an address translation method and system for a KV storage device. The provided address translation method for a read operation for a KV storage device includes: obtaining a logical address accessed by a read operation; and if the logical address hits a cached translation page, obtaining a physical address corresponding to the logical address from the cached translation page.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: September 20, 2022
    Assignee: BEIJING MEMBLAZE TECHNOLOGY CO., LTD
    Inventors: Qingtao Sun, Cong Sun, Junwei Hou
  • Patent number: 11442669
    Abstract: A method of orchestrating a virtual storage system, the method comprising: determining a change to one or more resource demands; determining, based on the change to the one or more resource demands, one or more modifications to one or more virtual components included as part of a virtual storage system architecture of a virtual storage system within a cloud computing environment; and initiating, responsive to the change to the one or more resource demands, the one or more modifications to the one or more virtual components included as part of the virtual storage system architecture of the virtual storage system.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 13, 2022
    Assignee: Pure Storage, Inc.
    Inventors: Yuval Frandzel, Naveen Neelakantam
  • Patent number: 11422944
    Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: August 23, 2022
    Assignee: Intel Corporation
    Inventors: Kaijie Guo, Weigang Li, Junyuan Wang, Liang Ma, Maksim Lukoshkov, Yao Huo
  • Patent number: 11416394
    Abstract: A memory management method, apparatus, and system are provided. The memory management method is performed by a memory management hardware accelerator, and the memory management hardware accelerator is coupled to an application subsystem and a communications subsystem. The application subsystem is configured to run a main operating system, and the communications subsystem is configured to run a communications operating system. The method includes: obtaining a set of memory addresses corresponding to dynamic memory space allocated by the main operating system to the communications subsystem, where the set of memory addresses includes one or more memory addresses; and sending some memory addresses in the set of memory addresses to a component of the communications subsystem.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: August 16, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yuelong Wang, Xinzhu Wang, Zhiguo Tu, Shaohua Wang
  • Patent number: 11409465
    Abstract: A system manages communication between a non-volatile memory express-over fabric (NVMe-oF) host unit and multiple non-volatile memory express-solid state drive (NVMe-SSD) storage devices via a bridge unit. The bridge unit may include sub-modules to control operations. The bridge unit may generate a virtual data memory address corresponding to a scattered gathered list address. The bridge unit may not require a data buffer to store intermediate data. The system may be configured to initiate a memory WRITE/READ transaction to access a virtual data memory corresponding to a physical memory in the bridge unit for performing a data WRITE/READ operation by an NVMe-SSD storage device.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 9, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Venkataratnam Nimmagadda, Anil Desmal Solanki
  • Patent number: 11403034
    Abstract: In an approach to NV SCM data flow with mismatched block sizes, responsive to receiving a command from a host on a memory controller for a storage class memory, whether the command is a write command is determined. Responsive to determining that the command is the write command, the command is inserted into a first buffer. Responsive to the command exiting the first buffer, whether the command generates a cache hit from the internal cache is determined. Responsive to determining that the command generates the cache hit, the write data is written into the internal cache. Responsive to determining that the command does not generate the cache hit, whether an oldest page in the internal cache is dirty is determined. Responsive to determining that the oldest page in the internal cache is dirty, a modified oldest page is written to the internal cache and a second buffer.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: August 2, 2022
    Assignee: International Business Machines Corporation
    Inventors: Daniel Frank Moertl, Robert Edward Galbraith, Damir Anthony Jamsek
  • Patent number: 11397543
    Abstract: Timed memory access, including: determining, in response to a memory access request, based on a time value, an entry in an access permissions table; and determining, based on the entry, whether to allow the memory access request that can include determining, based on a modulo of the time value and a number of entries in the access permissions table, a table index and determining, based on the table index, the entry.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 26, 2022
    Assignee: Ghost Locomotion Inc.
    Inventors: John Hayes, Volkmar Uhlig, Richard A. Swetz, Daniel P. Potts, Aaron Carroll
  • Patent number: 11392515
    Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: July 19, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dionisio Minopoli, Daniele Balluchi
  • Patent number: 11392529
    Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: July 19, 2022
    Assignee: United States of America as represented by the Secretary of the Air Force
    Inventors: Mark H Linderman, Qing Wu, Dennis Fitzgerald
  • Patent number: 11392329
    Abstract: Two data storage systems, DS1 and DS2, may be initially configured with identifiers for target ports and target port groups. Subsequently, the two system may be combined into a cluster including a stretched volume configured from the volumes V1 and V2, respectively, on DS1 and DS2, where V1 and V2 are exposed to the host as the same logical volume, L1, over multiple paths from DS1 and DS2 to the host. V1 may have a normal attribute indicating target ports and port groups of DS1 have associated identifiers as specified in an initial configuration when reporting information regarding L1 to the host. V2 may have an extended attribute indicating that target ports and port groups of DS2 have associated extended identifiers determined using a first extended value and using identifiers from an initial configuration when reporting information regarding L1 to the host.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: July 19, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Dmitry Tylik, Dave J. Lindner, Carole Ann Gelotti, Matthew Long
  • Patent number: 11379149
    Abstract: A semiconductor device may include a memory controller, which may include a request queue storing requests. Requests include a memory request including a read request to a memory device or a write request to the memory device, and a process in memory (PIM) request requesting a processing operation in the memory device. The memory controller may also include a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue, a command queue storing a memory command and a PIM command output from the command generator, and a command scheduler configured to control output order, output timing, or both of a memory command and a PIM command stored in the command queue.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: July 5, 2022
    Assignees: SK HYNIX INC., KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION
    Inventors: Seon Wook Kim, Wonjun Lee, Changhyun Kim
  • Patent number: 11360708
    Abstract: Technologies are provided for supporting storage device write barriers. A storage device can be configured to associate a data access command with a write barrier. The write barrier can be used to indicate that one or more data access commands should be processed before one or more other data access commands are processed. For example, a host computer can transmit one or more data access commands to a storage device. The storage device can determine that the one or more data access commands are associated with a write barrier. The host computer can continue to transmit additional data access commands to the storage device. However, the storage device will not process the additional data access commands until after the one or more data access commands associated with the write barrier have been processed.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 14, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Munif M. Farhan, Keun Soo Jo, James Alexander Bornholt, Andrew Kent Warfield, Andrew C. Schleit, Seth W. Markle
  • Patent number: 11360906
    Abstract: The devices within an inter-device processing system maintain data coherency in the last level caches of the system as a cache line of data is shared between the devices by utilizing a directory in one of the devices that tracks the coherency protocol states of the memory addresses in the last level caches of the system.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: June 14, 2022
    Assignee: Alibaba Group Holding Limited
    Inventors: Lide Duan, Hongyu Liu, Hongzhong Zheng, Yen-Kuang Chen
  • Patent number: 11347654
    Abstract: A storage device includes a nonvolatile memory device and a memory controller. After writing first data at the first page, the memory controller writes second data at a second page. The memory controller generates first check data corresponding to the first data and second check data corresponding to the second data. The memory controller recovers the first and second physical addresses and the first and second logical addresses based on the second check data.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: May 31, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Heechul Chae
  • Patent number: 11340830
    Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert Nasry Hasbun, Dean D. Gans, Sharookh Daruwalla
  • Patent number: 11334515
    Abstract: A method for enabling and disabling Port Error detection and customizing corresponding error count threshold values. The method allows for adjustment of signal error verification thresholds before a connected port signals a loss of connection due to corrupted characters detected during normal operation and initialization on an IEEE-1394 serial bus. Also, the method customizes the limits for a Loss of Synchronization transition and reduces the probability for Bus Resets. Further, the method provides for a more stable bus operation, which is critical for usage in tight-looped and low-latency control systems.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: May 17, 2022
    Inventor: Michael Erich Vonbank
  • Patent number: 11328755
    Abstract: A data producer stores input data in a buffer in response to a slow clock signal and provides read data from the buffer in response to a read pointer signal. A data movement circuit reads the input data from the buffer using the read pointer signal and provides an update read pointer signal in response to reading the input data. The data movement circuit operates in response to a fast clock signal, and includes a metastable-free synchronizer circuit having inputs for receiving the update read pointer signal, the slow clock signal, and the read pointer signal, and an output for providing a synchronized read pointer signal equal to the read pointer signal except between a change in the read pointer signal while the slow clock signal is active until an inactivation of the slow clock signal. The buffer provides the read data in response to the synchronized read pointer signal.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: May 10, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Arjun Singhal, Subrata Roy
  • Patent number: 11301411
    Abstract: A port of a computing device includes protocol circuitry to implement a particular interconnect protocol, where the protocol circuitry is to generate a set of ordered sets defined according to the particular interconnect protocol. The set of ordered sets is generated for a link to couple a first device to a second device and the set of ordered sets comprises link information for the link. Translation layer circuitry is provided to: generate, from the set of ordered sets, at least one data structure to comprise at least a portion of the link information, and cause the data structure to be sent from the first device to the second device on the link in lieu of the set of ordered sets.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: April 12, 2022
    Assignee: Intel Corporation
    Inventor: David J. Harriman
  • Patent number: 11281593
    Abstract: Provided are a computer program product, system, and method for using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors. A plurality of insertion points to a cache list for the shared cache having a least recently used (LRU) end and a most recently used (MRU) end identify tracks in the cache list. For each processor, of a plurality of processors, for which indication of tracks accessed by the processor is received, a determination is made of insertion points of the provided insertion points at which to indicate the tracks for which indication is received. The tracks are indicated at positions in the cache list with respect to the determined insertion points.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: March 22, 2022
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Kyler A. Anderson, Kevin J. Ash, Matthew J. Kalos
  • Patent number: 11275679
    Abstract: Methods, systems, and devices for separate cores for media management of a memory sub-system are described. A controller of a memory sub-system can include a first processing core and a second processing core for a garbage collection procedure. The first processing core can perform a first set of one or more operations associated with a read process of a first stage of a garbage collection procedure for a plurality of transfer units of the memory sub-system. The second processing core can perform a second set of one or more operations associated with a write process of the first stage of the garbage collection procedure, where the second set of one or more operations are concurrent with the first set of one or more operations.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Antonio David Bianco, John Paul Traver