Abstract: A memory controller includes a memory channel controller that uses multiple groups of command queue and arbiter pairs. Each arbiter is coupled to a respective command queue to select memory access commands from each command queue according to predetermined criteria. Each arbiter selects from among the memory access requests in each command queue independently based on the predetermined criteria and sends selected memory access requests to a selector that serves as a second level arbiter which sends the request to a memory subchannel.

Abstract: A system and method for efficiently storing and accessing large volumes of metadata persistent on Non-Volatile Memory (NVM) storage systems is provided. The system applies log-structured, Copy-on-Write (CoW) B+ tree methods, and supports a core-affine data and resource partitioning approaches on the system's architecture and platform with a high-degree of parallelism within the CPU, NVMe storage, and networking devices. The subject system and method efficiently indexes both in-core (DRAM resident) and out-of-core (NVM resident) metadata, supports a variety of data access patterns, supports CoW features and provides verifiable data safety and integrity capabilities. The present system minimizes latencies over all aspects of the metadata management and access path by leveraging core-affine resource partitioning with runtime environment providing lightweight user-level threads with low-latency context switching that execute within the exclusive context of a dedicated CPU core, and partitioned resources.

Abstract: Embodiments of the present invention provide a computer system, a computer program product, and a method that comprises collecting data capable of being replicated from a computing device; detecting risks of the computing device, wherein detecting risks comprises detecting the computing device's surroundings, location, speed, and condition; initiating data replication on the computing device once the risks are determined to reach a predetermined threshold; and storing the replicated data within a cloud storage system using a 5G network.

Abstract: An integrated circuit (IC) includes a memory manager having a plurality of memory ports, each configured to communicate with a corresponding floating memory block. The IC includes a first interconnect for a first domain, wherein the first interconnect has a first set of fixed ports configured to communicate with memory blocks dedicated to the first domain and a first set of floating ports configured to communicate with the memory manager, and a second interconnect for a second domain, wherein the second interconnect has a second set of fixed ports configured to communicate with memory blocks dedicated to the second domain and a second set of floating ports configured to communicate with the memory manager. The memory manager is configured to allocate a first portion of the memory ports to the first set of floating ports and a second portion of the memory ports to the second set of floating ports.

Abstract: A host device and memory device perform internal write leveling of a data strobe with a write command. The memory device includes an input-output interface that receives the data strobe from the host device. The memory device also includes internal write circuitry configured to launch an internal write signal. The internal write circuitry includes an emulation loop configured to emulate circuitry in a clock path of a write clock generated from the clock and used to generate a feedback clock. The internal write circuitry includes a write delay lock loop configured to receive the write clock and the feedback clock to determine a number of cycles used for the loop, transmit the number of cycles to the host device to be used as a cycle adjust in an internal write leveling process, and complete the internal write leveling process with the host device using the cycle adjust.

Abstract: The present application provides an address translation method and system for a KV storage device. The provided address translation method for a read operation for a KV storage device includes: obtaining a logical address accessed by a read operation; and if the logical address hits a cached translation page, obtaining a physical address corresponding to the logical address from the cached translation page.

Abstract: A method of orchestrating a virtual storage system, the method comprising: determining a change to one or more resource demands; determining, based on the change to the one or more resource demands, one or more modifications to one or more virtual components included as part of a virtual storage system architecture of a virtual storage system within a cloud computing environment; and initiating, responsive to the change to the one or more resource demands, the one or more modifications to the one or more virtual components included as part of the virtual storage system architecture of the virtual storage system.

Abstract: Examples herein relate to a system that includes a first memory device; a second memory device; and an input-output memory management unit (IOMMU). The IOMMU can search for a virtual-to-physical address translation entry in a first table for a received virtual address and based on a virtual-to-physical address translation entry for the received virtual address not being present in the first table, search a second table for a virtual-to-physical address translation entry for the received virtual address, wherein the first table is stored in the first memory device and the second table is stored in the second memory device. In some examples, based on a virtual-to-physical address translation entry for the received virtual address not being present in the second table, a page table walk is performed to determine a virtual-to-physical address translation for the received virtual address. In some examples, the first table includes an IO translation lookaside buffer (IOTLB).

Abstract: A memory management method, apparatus, and system are provided. The memory management method is performed by a memory management hardware accelerator, and the memory management hardware accelerator is coupled to an application subsystem and a communications subsystem. The application subsystem is configured to run a main operating system, and the communications subsystem is configured to run a communications operating system. The method includes: obtaining a set of memory addresses corresponding to dynamic memory space allocated by the main operating system to the communications subsystem, where the set of memory addresses includes one or more memory addresses; and sending some memory addresses in the set of memory addresses to a component of the communications subsystem.

Abstract: A system manages communication between a non-volatile memory express-over fabric (NVMe-oF) host unit and multiple non-volatile memory express-solid state drive (NVMe-SSD) storage devices via a bridge unit. The bridge unit may include sub-modules to control operations. The bridge unit may generate a virtual data memory address corresponding to a scattered gathered list address. The bridge unit may not require a data buffer to store intermediate data. The system may be configured to initiate a memory WRITE/READ transaction to access a virtual data memory corresponding to a physical memory in the bridge unit for performing a data WRITE/READ operation by an NVMe-SSD storage device.

Abstract: In an approach to NV SCM data flow with mismatched block sizes, responsive to receiving a command from a host on a memory controller for a storage class memory, whether the command is a write command is determined. Responsive to determining that the command is the write command, the command is inserted into a first buffer. Responsive to the command exiting the first buffer, whether the command generates a cache hit from the internal cache is determined. Responsive to determining that the command generates the cache hit, the write data is written into the internal cache. Responsive to determining that the command does not generate the cache hit, whether an oldest page in the internal cache is dirty is determined. Responsive to determining that the oldest page in the internal cache is dirty, a modified oldest page is written to the internal cache and a second buffer.

Abstract: Timed memory access, including: determining, in response to a memory access request, based on a time value, an entry in an access permissions table; and determining, based on the entry, whether to allow the memory access request that can include determining, based on a modulo of the time value and a number of entries in the access permissions table, a table index and determining, based on the table index, the entry.

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being by-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

Abstract: Two data storage systems, DS1 and DS2, may be initially configured with identifiers for target ports and target port groups. Subsequently, the two system may be combined into a cluster including a stretched volume configured from the volumes V1 and V2, respectively, on DS1 and DS2, where V1 and V2 are exposed to the host as the same logical volume, L1, over multiple paths from DS1 and DS2 to the host. V1 may have a normal attribute indicating target ports and port groups of DS1 have associated identifiers as specified in an initial configuration when reporting information regarding L1 to the host. V2 may have an extended attribute indicating that target ports and port groups of DS2 have associated extended identifiers determined using a first extended value and using identifiers from an initial configuration when reporting information regarding L1 to the host.

Abstract: An apparatus for a microprocessor computer system and method for configuring the same where said microprocessor computer system comprises a processor core and at least one hardware buffer FIFO with memory-mapped head and tail that handles data movement among the processor cores, networks, raw data input and outputs, and memory. The method for configuring said microprocessor computer system comprises utilizing a FIFO auxiliary processor to process said data traversing said hardware FIFO; utilizing said hardware FIFOs to efficiently pipe data through functional blocks; and utilizing a FIFO controller to perform DMA operations that include non-unit-stride access patterns and transfers among processor cores, networks, raw data input and outputs, memory, and other memory-mapped hardware FIFOs.

Abstract: A semiconductor device may include a memory controller, which may include a request queue storing requests. Requests include a memory request including a read request to a memory device or a write request to the memory device, and a process in memory (PIM) request requesting a processing operation in the memory device. The memory controller may also include a command generator configured to generate a memory command from a memory request output from the request queue and to generate a PIM command from a PIM request output from the request queue, a command queue storing a memory command and a PIM command output from the command generator, and a command scheduler configured to control output order, output timing, or both of a memory command and a PIM command stored in the command queue.

Abstract: The devices within an inter-device processing system maintain data coherency in the last level caches of the system as a cache line of data is shared between the devices by utilizing a directory in one of the devices that tracks the coherency protocol states of the memory addresses in the last level caches of the system.

Abstract: Technologies are provided for supporting storage device write barriers. A storage device can be configured to associate a data access command with a write barrier. The write barrier can be used to indicate that one or more data access commands should be processed before one or more other data access commands are processed. For example, a host computer can transmit one or more data access commands to a storage device. The storage device can determine that the one or more data access commands are associated with a write barrier. The host computer can continue to transmit additional data access commands to the storage device. However, the storage device will not process the additional data access commands until after the one or more data access commands associated with the write barrier have been processed.

Abstract: A storage device includes a nonvolatile memory device and a memory controller. After writing first data at the first page, the memory controller writes second data at a second page. The memory controller generates first check data corresponding to the first data and second check data corresponding to the second data. The memory controller recovers the first and second physical addresses and the first and second logical addresses based on the second check data.

Abstract: Methods, systems, and devices for memory buffer management and bypass are described. Data corresponding to a page size of a memory array may be received at a virtual memory bank of a memory device, and a value of a counter associated with the virtual memory bank may be incremented. Upon determining that a value of the counter has reached a threshold value, the data may be communicated from the virtual memory bank to a buffer of the same memory device. For instance, the counter may be incremented based on the virtual memory bank receiving an access command from a host device.