Abstract: A storage system, blades, removable modules, and method of configuring a storage system are described. The storage system has blades with computing resources and storage resources. At least one of the blades has, or has added, one or more removable modules.

Abstract: A system is disclosed. An upstream interface enables communication with a processor; a downstream interface enables communication with a storage device. The system may also include an acceleration module implemented using hardware to execute an acceleration instruction. The storage device may include an endpoint of the storage device for communicating with the acceleration module, a controller to manage operations of the storage device, storage for data, and a storage device acceleration module to assist the acceleration module in executing the acceleration instruction.

Abstract: The present disclosure generally relates to host memory buffer (HMB) cache management. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.

Abstract: Technologies for processing network packets by a host interface of a network interface controller (NIC) of a compute device. The host interface is configured to retrieve, by a symmetric multi-purpose (SMP) array of the host interface, a message from a message queue of the host interface and process, by a processor core of a plurality of processor cores of the SMP array, the message to identify a long-latency operation to be performed on at least a portion of a network packet associated with the message. The host interface is further configured to generate another message which includes an indication of the identified long-latency operation and a next step to be performed upon completion. Additionally, the host interface is configured to transmit the other message to a corresponding hardware unit scheduler as a function of the subsequent long-latency operation to be performed. Other embodiments are described herein.

Abstract: The present application relates to a network-on-chip data processing method. The method is applied to a network-on-chip processing system, the network-on-chip processing system is used for executing machine learning calculation, and the network-on-chip processing system comprises a storage device and a calculation device. The method comprises: accessing the storage device in the network-on-chip processing system by means of a first calculation device in the network-on-chip processing system and obtaining first operation data; performing an operation on the first operation data by means of the first calculation device to obtain a first operation result; and sending the first operation result to a second calculation device in the network-on-chip processing system. According to the method, operation overhead can be reduced and data read/write efficiency can be improved.

Abstract: Symmetric storage using a cloud-based storage system, including: receiving, at a cloud-based storage system among storage systems synchronously replicating a dataset, an I/O operation directed to the dataset; determining, in dependence upon the I/O operation, a metadata update describing a mapping of segments of content to an address within a storage object, wherein the storage object includes the dataset; and synchronizing metadata on another storage system of the storage systems by sending the metadata update from the cloud-based storage system to the other storage system to update a metadata representation on the second storage system in accordance with the metadata update.

Abstract: A buffer chip includes a first interface to receive in-band register access commands from a host and a second interface to receive side-band register access commands from the host. The buffer chip further includes an arbitration circuit coupled to the first interface and to the second interface, wherein the arbitration circuit is to receive control signals from the first interface indicating a first pending register access command for the first interface, and wherein the arbitration circuit is to select the first pending register access command from concurrent pending register access commands from the first interface and the second interface using the control signals. In addition, the buffer chip includes a command buffer register coupled to the arbitration circuit, wherein the arbitration circuit to perform, on the command buffer register, a register access operation corresponding to the first pending register access command.

Abstract: An integrated-circuit memory component receives, as part of respective first and second memory read transactions, a first column access command that identifies a first volume of data and a second column read command that identifies a second volume of data, the second volume of data being constituted by not more than half as many data bits as the first volume of data. In response to receiving the first column access command, the integrated-circuit memory component transmits the first volume of data as N parallel bit-serial data signals over N external signaling links. In response to receiving the second column access command, the integrated-circuit memory component transmits the second volume of data as M parallel bit-serial data signals over M of the N external signaling links, where M is less than N.

Abstract: A semiconductor device is provided. The semiconductor device comprises a first memory unit including a first memory area, and a first logic area electrically connected to the first memory area, the first logic area including a cache memory and an interface port. The first memory unit executes a data transmission and reception operation with a memory unit adjacent to the first memory unit via the first interface port and the cache memory.

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

Abstract: A memory controller can receive transactions from an interconnect to access the memory. The memory controller can use a credit-based scheme to request the interconnect to send specific memory transactions that can be scheduled in a desirable order using a credit type associated with each transaction. In some embodiments, the memory controller can keep track of the number of transactions directed to each bank of the memory based on a credit type, so that specific transactions directed towards the underutilized banks can be requested and scheduled in a manner to utilize all the banks more uniformly to improve the system performance.

Abstract: A reconfigurable compute fabric of a system can include multiple nodes, and each node can include multiple, communicatively coupled tiles with respective processing and storage elements. In an example, a tile-based processor can be configured to perform operations comprising receiving a first stencil that defines input data for a first operation. The stencil can have a height corresponding to N rows in a main memory and a stencil width corresponding to M columns in the main memory. The processor can perform operations comprising establishing N buffers in a tile memory, each buffer having M buffer elements, and populating the M buffer elements of the N buffers using respective information, defined by the first stencil, from the main memory. Tile-based stencil operations can use information from the N buffers and provide compute results in an output array.

Abstract: Running an independent task in connection with a synchronous I/O operation between a storage system and a host includes starting the synchronous I/O operation, setting a timer for the synchronous I/O operation, starting the independent task that runs while waiting for completion of the synchronous I/O operation, and aborting the synchronous I/O operation in response to the timer expiring prior to completion of the synchronous I/O operation. The independent task may be ended in response to the timer expiring. The independent task may be ended in response to the I/O operation completing. The synchronous I/O operation may be performed using a high speed connection between the storage system and the host, which may be coupled to a smart network interface controller provided on a director board in the storage system. The smart network interface controller may include a system on a chip having a processor, memory, and non-volatile storage.

Abstract: The present disclosure relates to a method for improving the reading and/or writing phase in storage devices including a plurality of non-volatile memory portions managed by a memory controller, comprising: providing at least a faster memory portion having a lower latency and higher throughput with respect to said non-volatile memory portions and being bi-directionally connected to said controller; using said faster memory portion as a read and/or write cache memory for copying the content of memory regions including more frequently read or written logical blocks of said plurality of non-volatile memory portions. A specific read cache architecture for a managed storage device is also disclosed to implement the above method.

Abstract: A memory storage system comprising a non-volatile semiconductor memory device comprising a memory array and a plurality of buffers, and a controller in communication with the plurality of buffers. The controller may be configured to issue a command to the non-volatile semiconductor memory device to cause a transfer of a data payload from the controller to a subset of n first buffers of the plurality of buffers. The controller may also be configured to issue a command to the non-volatile semiconductor memory device to cause the non-volatile memory device to transfer a data payload from the memory array to a subset of n first buffers of the plurality of buffers.

Abstract: Servicing I/O operations in a cloud-based storage system, including: receiving, by the cloud-based storage system, a request to write data to the cloud-based storage system; storing, in solid-state storage of the cloud-based storage system, the data; storing, in object storage of the cloud-based storage system, the data; detecting that at least some portion of the solid-state storage of the cloud-based storage system has become unavailable; identifying data that was stored in the portion of the solid-state storage of the cloud-based storage system that has become unavailable; retrieving, from object storage of the cloud-based storage system, the data that was stored in the portion of the solid-state storage of the cloud-based storage system that has become unavailable; and storing, in solid-state storage of the cloud-based storage system, the retrieved data.

Abstract: Embodiments of the present disclosure provide a method, an electronic device, and a computer program product for data compression. The method includes: comparing the size of a first data packet to be compressed with a first threshold size; if the size of the first data packet is greater than the first threshold size, determining at least two second data packets from the first data packet, wherein the size of each second data packet is less than a second threshold size; and respectively compressing the at least two second data packets. In this way, the delay of data compression can be shortened.

Abstract: A technique for managing messaging between storage nodes of a storage system includes a first storage node delaying the sending of non-latency-critical messages to a second storage node until the first storage node has a latency-critical message to be sent. The technique further includes combining the non-latency-critical messages with the latency-critical message to form a single, aggregated message, and sending the aggregated message to the second storage node.

Abstract: A data processor includes a fabric-attached memory (FAM) interface for coupling to a data fabric and fulfilling memory access instructions. A requestor-side adaptive consistency controller coupled to the FAM interface requests notifications from a fabric manager for the fabric-attached memory regarding changes in requestors authorized to access a FAM region which the data processor is authorized to access. If a notification indicates that more than one requestor is authorized to access the FAM region, fences are activated for selected memory access instructions in a local application.