Patents Examined by Richard Booth
  • Patent number: 11631752
    Abstract: A semiconductor device include a substrate, a buffer layer formed on the substrate, a channel layer formed by an intrinsic polycrystalline silicon layer on the buffer layer, polycrystalline source and drain by non-intrinsic silicon formed on both sides of the polycrystalline silicon layer, a source electrode and a drain electrode formed on the polycrystalline source and the drain, a gate electrode corresponding to the channel layer, and an NiSi2 contact layer located between the source and the source electrode and between the drain and the drain electrode.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 18, 2023
    Inventor: Ying Hong
  • Patent number: 11626407
    Abstract: A method for manufacturing a dynamic random access memory device includes providing a semiconductor substrate and forming a highly doped diffusion region in a surface of the semiconductor substrate. A wordline structure is then deposited on the surface of the semiconductor substrate, where the wordline structure includes an electrically conductive gate layer. An opening is further formed in the wordline structure, where the opening is located at a first end of and extending to the highly doped diffusion region. A semiconductor pillar is then formed in the opening by selective epitaxial growth. An end of the semiconductor pillar is then doped and the doped end is connected with a memory element.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: April 11, 2023
    Assignee: Integrated Silicon Solution, (Cayman) Inc.
    Inventors: Andrew J. Walker, Dafna Beery, Peter Cuevas, Amitay Levi
  • Patent number: 11621373
    Abstract: The invention relates to an optoelectronic device (100) comprising a semiconductor layer sequence (1) on a carrier (7), the semiconductor layer sequence (1) comprising at least one n-doped semiconductor layer (11), at least one p-doped semiconductor layer (12) and an active layer (13) sandwiched between the p- and n-doped semiconductor layers (11, 12), an reconnecting contact (2), which is configured for electrically contacting the n-doped semiconductor layer (11), a p-connecting contact (3), which is configured for electrically contacting the p-doped semiconductor layer (12), the n-connecting contact (2) being arranged on the side of the semiconductor layer sequence (1) facing away from the carrier (7), the n-connecting contact (2) having a first side (4) which is arranged facing the semiconductor layer sequence (1), wherein the first side (4) has two outer regions (43) and an inner region (44), viewed in lateral cross-section, which is delimited by the outer regions (43), wherein the outer regions (43) of t
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: April 4, 2023
    Assignee: OSRAM OLED GMBH
    Inventor: Guido Weiss
  • Patent number: 11621194
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. A method includes forming a mask above the semiconductor wafer, the mask including a layer covering and protecting the integrated circuits. The mask and a portion of the semiconductor wafer are patterned with a laser scribing process to provide a patterned mask and to form trenches partially into but not through the semiconductor wafer between the integrated circuits. Each of the trenches has a width. The semiconductor wafer is plasma etched through the trenches to form corresponding trench extensions and to singulate the integrated circuits. Each of the corresponding trench extensions has the width.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: April 4, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Brad Eaton, Madhava Rao Yalamanchili, Saravjeet Singh, Ajay Kumar, James M. Holden
  • Patent number: 11610903
    Abstract: Various aspects relate to a functional layer and the formation thereof. A method for manufacturing a functional layer of an electronic device may include: forming a plurality of sublayers of the functional layer by a plurality of consecutive sublayer processes, each sublayer process of the plurality of consecutive sublayer processes comprising: forming a sublayer of the plurality of sublayers by vapor deposition, the sublayer comprising one or more materials, and, subsequently, crystallizing the one or more materials comprised in the sublayer.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: March 21, 2023
    Assignee: FERROELECTRIC MEMORY GMBH
    Inventor: Tony Schenk
  • Patent number: 11610964
    Abstract: A method of manufacturing a capacitor structure of memory, including forming a patterned photoresist layer on a hard mask layer and spacers on sidewalls of the patterned photoresist layer, perform a first etch process to remove uncovered hard mask layer so as to form first patterned hard mask layer and expose first portion of the dielectric layer, lowering a surface of the first portion of dielectric layer, perform a second etch process to remove uncovered first patterned hard mask layer so as to form second patterned hard mask layer and expose second portion of the dielectric layer, and performing a hole etching process to form first holes and second holes respectively in the first portion and the second portion of dielectric layer, wherein sidewalls of the first holes and second holes have wavelike cross-sections, and the wavelike cross-sections of first holes and second holes are shifted vertically by a distance.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: March 21, 2023
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Kai-Jyun Huang
  • Patent number: 11611001
    Abstract: A layered structure (100) for transmission of an acoustic wave, the layered structure (100) comprising: a substrate layer (102); and a second layer (104) over the substrate layer (102), wherein the second layer (104) comprises a plurality of discrete portions (105) adjacent to each other, each discrete portion (105) of the plurality of discrete portions (105) comprising a first subregion (104A) and a second subregion (104B). Also an epitaxial layer (108), grown over the second layer (104), for transmission of the acoustic wave in a major plane of the epitaxial layer (108), wherein a periodicity (?) of a wavelength of the acoustic wave to be transmitted through the epitaxial layer (108) is approximately equal to a sum of a width (dA) of the first subregion (104A) and a width (dB) of the second subregion (104B).
    Type: Grant
    Filed: April 14, 2021
    Date of Patent: March 21, 2023
    Assignee: IQE plc
    Inventors: Andrew Clark, Rodney Pelzel, Richard Hammond
  • Patent number: 11610820
    Abstract: Semiconductor devices and methods of manufacturing the same are provided. The semiconductor devices may have a memory array having two transistor (2T) memory cells, each including a non-volatile memory (NVM) transistor and a high voltage (HV) field-effect transistor (FET) as a select transistor. The devices further include a logic area in which HV FETs, input/output (I/) FETs, and low voltage (LV)/core FETs are formed thereon. Other embodiments are also described.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 21, 2023
    Assignee: Infineon Technologies LLC
    Inventors: Krishnaswamy Ramkumar, Venkatraman Prabhakar
  • Patent number: 11611000
    Abstract: There is provided a nonvolatile storage element having excellent charge holding characteristics capable of reducing variations in electric characteristics and an analog circuit provided with the same. A nonvolatile storage element is provided with a charge holding region and an insulator surrounding the entire surface of the charge holding region and having halogen distributed in at least one part of a region surrounding the entire surface.
    Type: Grant
    Filed: October 3, 2017
    Date of Patent: March 21, 2023
    Assignee: Asahi Kasei Microdevices Corporation
    Inventors: Toshiro Sakamoto, Satoshi Takehara, Yoshiro Yamaha, Makoto Kobayashi
  • Patent number: 11605541
    Abstract: Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: March 14, 2023
    Assignee: AKHAN SEMICONDUCTOR, INC.
    Inventor: Adam Khan
  • Patent number: 11605723
    Abstract: Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: March 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Scott E. Sills, Durai Vishak Nirmal Ramaswamy
  • Patent number: 11605750
    Abstract: Solar cells having emitter regions composed of wide bandgap semiconductor material are described. In an example, a method includes forming, in a process tool having a controlled atmosphere, a thin dielectric layer on a surface of a semiconductor substrate of the solar cell. The semiconductor substrate has a bandgap. Without removing the semiconductor substrate from the controlled atmosphere of the process tool, a semiconductor layer is formed on the thin dielectric layer. The semiconductor layer has a bandgap at least approximately 0.2 electron Volts (eV) above the bandgap of the semiconductor substrate.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: March 14, 2023
    Assignee: SunPower Corporation
    Inventors: Richard M. Swanson, Marius M. Bunea, Michael C. Johnson, David D. Smith, Yu-Chen Shen, Peter J. Cousins, Tim Dennis
  • Patent number: 11605561
    Abstract: Implementations of methods of singulating a plurality of die included in a substrate may include forming a groove through a backside metal layer through laser ablating a backside metal layer at a die street of a substrate and singulating a plurality of die included in the substrate through removing substrate material of the substrate in the die street.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: March 14, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Michael J. Seddon
  • Patent number: 11594612
    Abstract: The present disclosure provides a method of forming a semiconductor device including an nFET structure and a pFET structure where each of the nFET and pFET structures include a semiconductor substrate and a gate trench. The method includes depositing an interfacial layer in each gate trench; depositing a first metal oxide layer over the interfacial layer; removing the first metal oxide layer from the pFET structure; depositing a ferroelectric layer in each gate trench; depositing a second metal oxide layer over the ferroelectric layer; removing the second metal oxide layer from the nFET structure; and depositing a gate electrode in each gate trench.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Min Cao, Pei-Yu Wang, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 11587838
    Abstract: A grinding control method and device for a wafer, and a grinding device are provided. A grinder is controlled to grind a mass production wafer with a set grinding parameter. In a case that it is determined to perform a test using a test wafer, the grinder may be controlled to grind the test wafer with the set grinding parameter. A first total thickness variation of the grinded test wafer is acquired by a dedicated measurement device, and an updated grinding parameter is acquired based on the first total thickness variation. The grinder is controlled to grind the mass production wafer with the updated grinding parameter. In this way, a wafer with a uniform thickness can be obtained, thereby improving flatness of the grinded wafer.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: February 21, 2023
    Assignee: Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
    Inventors: Hongsheng Yi, Zhijun Zhang, Yifan Yang
  • Patent number: 11587864
    Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: February 21, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Poornika Fernandes, Ye Shao, Guruvayurappan S. Mathur, John K. Arch, Paul Stulik
  • Patent number: 11578425
    Abstract: In various embodiments, controlled heating and/or cooling conditions are utilized during the fabrication of aluminum nitride single crystals and aluminum nitride bulk polycrystalline ceramics. Thermal treatments may also be utilized to control properties of aluminum nitride crystals after fabrication.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 14, 2023
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Jianfeng Chen, Keisuke Yamaoka, Shichao Wang, Shailaja P. Rao, Takashi Suzuki, Leo J. Schowalter
  • Patent number: 11574904
    Abstract: In an embodiment, a semiconductor device is provided that includes a main transistor having a load path, a sense transistor configured to sense a main current flowing in the load path of the main transistor, and at least one bypass diode structure configured to protect the sense transistor. The at least one bypass diode structure is electrically coupled in parallel with the sense transistor.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: February 7, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Florian Gasser
  • Patent number: 11575000
    Abstract: A method for manufacturing a vertical JFET includes providing a III-nitride substrate having a first conductivity type; forming a first III-nitride layer coupled to the III-nitride substrate, wherein the first III-nitride layer is characterized by a first dopant concentration and the first conductivity type; forming a plurality of trenches within the first III-nitride layer, wherein the plurality of trenches extend to a predetermined depth; epitaxially regrowing a second III-nitride structure in the trenches, wherein the second III-nitride structure is characterized by a second conductivity type; forming a plurality of III-nitride fins, each coupled to the first III-nitride layer, wherein the plurality of III-nitride fins are separated by one of a plurality of recess regions; epitaxially regrowing a III-nitride gate layer in the recess regions, wherein the III-nitride gate layer is coupled to the second III-nitride structure, and wherein the III-nitride gate layer is characterized by the second conductivity t
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: February 7, 2023
    Assignee: NEXGEN POWER SYSTEMS, INC.
    Inventors: Hao Cui, Clifford Drowley
  • Patent number: 11574937
    Abstract: A peeling method at low cost with high mass productivity is provided. A silicon layer having a function of releasing hydrogen by irradiation with light is formed over a formation substrate, a first layer is formed using a photosensitive material over the silicon layer, an opening is formed in a portion of the first layer that overlaps with the silicon layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the silicon layer, the silicon layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: February 7, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masataka Sato, Masakatsu Ohno, Seiji Yasumoto, Hiroki Adachi