Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction “MCSST D1” is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer “0x0000_00FF”. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is “ON”. The multiplexer 24 outputs one of the maximum value “0x0000_00FF” generated by the constant generator 21, the zero value “0x0000_0000” generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Abstract: A processor (100) includes an issue unit (125) having an issue queue (144) for issuing instructions to an execution unit (140). The execution unit (140) may accept and execute the instruction or produce a reject signal. After each instruction is issued, the issue queue (144) retains the issued instruction for a critical period. After the critical period, the issue queue (144) may drop the issued instruction unless the execution unit (140) has generated a reject signal. If the execution unit (140) has generated a reject signal, the instruction is eventually marked in the issue queue (144) as being available to be reissued. The length of time that the rejected instruction is held from reissue may be modified depending upon the nature of the rejection by the execution unit (140). Also, the execution unit (140) may conduct corrective actions in response to certain reject conditions so that the instruction may be fully executed upon reissue.

Abstract: A compression scheme for program executables that run in a reduced instruction set computer (RISC) architecture such as the PowerPC is disclosed. The method and system utilize scope-based compression for increasing the effectiveness of conventional compression with respect to register and literal encoding. First, discernible patterns are determined by exploiting instruction semantics and conventions that compilers adopt in register and literal usage. Additional conventions may also be set for register usage to facilitate compression. Using this information, separate scopes are created such that in each scope there is a more prevalent usage of a limited set of registers or literal value ranges, or there is an easily discernible pattern of register or literal usage. Each scope then is compressed separately by a conventional compressor.

Abstract: The disclosed is an improved superscalar processor for reducing the time required for execution of an instruction. The superscalar processor includes an instruction fetching stage, an instruction decoding stage, and function units each having a pipeline structure. A function unit includes an execution stage, a memory access stage, and a write back stage. Function units are connected through a newly provided bypass line. Data obtained by preceding execution in the other function unit (the other pipeline) is applied through the bypass line to a function unit (pipeline) for executing a later instruction. Executed data is transmitted between pipelines without through a register file, so that it becomes unnecessary for the pipeline requesting the executed data to wait for termination of execution of the other pipeline. As a result, time required for execution of an instruction is reduced.

Abstract: A processor (92) in a data processing system (80) provides a DELAY instruction. Executing the DELAY instruction causes the processor (92) to a specified integral number of clock (98) cycles before continuing. Delays are guaranteed to have a linear relationship with a constant slope with the specified number of clock cycles. Incrementing the specified delay through a range allows exhaustive testing of interactions among multiple processors.

Abstract: A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.

Abstract: A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A microprocessor uses a set of program instructions to select a memory configuration for retrieving the program instructions. The program memory stores the set of program instructions such that the microprocessor can retrieve the set of program instructions regardless of which bit-width is used to store the set of program instructions. Additional circuitry maps the address signals for retrieving the program instructions from the program memory.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads form memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: When a subroutine call instruction is transferred from the instruction memory 39 to the IDB 29 and decoded by the decoder 18, the following operations (1)-(3) are executed in parallel: (1) a return address storage operation for incrementing the value stored in the PC 15 using the INC 16 and for storing the incremented value in the LR 13 as a return address; (2) a branch operation for storing the entry address of the subroutine included in the subroutine call instruction in the PC 15; and (3) a stack reserve operation for preparing for the following use of a stack area by adding a value “−4” to the value stored in the SP 12 using the adder 22 and for storing the addition result in the SP 12.

Abstract: A method and apparatus for converting a packed integer data item having first and second data elements, to a packed floating-point data item. In one embodiment, a method includes moving the first data element of the integer data item to a first data element of a first intermediate data item and extending a sign of the first data element into all bit positions of a second data element of the first intermediate data item. The method further includes moving the second data element of the integer data item to a first data element of a second intermediate data item and extending a sign of the second data element into all bit positions of a second data element of the second intermediate data item. The first and second intermediate data items are converted from integer data items to respective floating-point data items, and the first and second intermediate floating-point data items are packed to first and second data elements of a result.

Abstract: An apparatus and method are provided for executing a push all/pop all instruction in a pipeline microprocessor. The apparatus includes an instruction buffer and a translator. The instruction buffer provides the push all/pop all instruction, directing the microprocessor to store/retrieve multiple operands to/from a stack. The translator generates a sequence of micro instructions to store/retrieve the multiple operands. Accesses to a pair of operands which are together aligned are combined into a single access.

Abstract: A microprocessor and a data processor therefor which have separate data and instruction buses, and wherein a data address and an instruction address are output over a single address bus in a time-shared manner, thereby allowing a data access and an instruction access to be pipelined without the need for separate address buses between the microprocessor and caches holding data and instructions.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Abstract: An apparatus is provided for sampling instructions in a processor pipeline of a computer system. The pipeline has a plurality of processing stages. Instructions are fetched into a first stage of the pipeline. A subset of the fetched instructions are identified as selected instructions. Event, latency, and state information of the system is sampled while any of the selected instructions are in any stage of the pipeline. Software is informed whenever any of the selected instructions leaves the pipeline to read the event and latency information.

Abstract: A communication control system and a method of implementing a high-speed data transmitting and receiving process uses a communication protocol program, a protocol buffer which is managed by the communication protocol program, a communication controller for controlling a transmission line and a network buffer managed by the communication controller. Further, there is provided a shared-buffer which is shared by the protocol buffer and a communication buffer. Frame data from a transmission line is shared by the shared-buffer, so that the frame data is directly written to and read from the shared-buffer by means of a shared-buffer control. Since the buffer is shared between the transmission line and the protocol, no excessive movement of data is required, thereby improving the throughput of the communication system as a whole.

Abstract: A cache memory configured to access stored instructions according to basic blocks is disclosed. Basic blocks are natural divisions in instruction streams resulting from branch instructions. The start of a basic block is a target of a branch, and the end is another branch instruction. A microprocessor configured to use a basic block oriented cache may comprise a basic block cache and a basic block sequence buffer. The basic block cache may have a plurality of storage locations configured to store basic blocks. The basic block sequence buffer also has a plurality of storage locations, each configured to store a block sequence entry. The block sequence entry may comprise an address tag and one or more basic block pointers. The address tag corresponds to the fetch address of a particular basic block, and the pointers point to basic blocks that follow the particular basic block in a predicted order.

Abstract: To accelerate read operations, or the operations that modify the operating parameters of a microcontroller, an interface is provided with three registers—an address register, an instruction and data register, and an auxiliary register. The instruction and data register supports the auxiliary register by indirect addressing. The address register is furthermore provided with an incrementation circuit mechanism for indirect incrementation. With the indirect addressing and the automatic incrementation, the number of external operations are reduced for continuous read or write operations.

Abstract: A shared bus system having a bus and a set of client modules coupled to the bus. Each client module is capable of sending transactions on the bus to other client modules and receiving transactions on the bus from other client modules for processing. Each module has a queue for storing transactions received by the module for processing. A bus controller limits the types of transactions that can be sent on the bus to prevent any module's queue from overflowing.