Abstract: A computer processor which has a apparatus in its Execution Unit (E-unit) that detects a match between an opcode about to be executed and opcodes programmed into it by the computer manufacturer provides a method for alleviating design deficiencies in the processor. The E-unit further contains a mechanism for transmitting the opcode and a desired action back to the Instruction Unit (I-unit) where it may be compared with the next instruction that is decoded. Furthermore, the E-unit opcode compare logic contains a mechanism for breaking infinite loops that may result. This E-unit opcode compare mechanism, may also be used for other purposes such as detecting invalid opcodes and other exception checking since it may allow for a faster cycle time of the processor than if this logic were implemented in the I-unit.

Abstract: A method of operation in a microprocessor is provided. A return address cache (RAC) is initialized. The RAC includes a portion to store predicted subroutine return addresses (PSRA) and first and second corresponding cache portions to store retired most recently updated (RMRU) ages of the PSRA and speculative most recently updated (SMRU) ages of the PSRA respectively. A PSRA is stored in a portion of the RAC corresponding to a first SMRU age and the SMRU ages are incremented responsive to prediction of a call instruction. A PSRA is read from a portion of the RAC corresponding to a second SMRU age and the SMRU ages are decremented responsive to prediction of a return instruction. Also a microprocessor that includes a return address cache (RAC) is provided. The RAC includes first and second tag portions to store retired most recently updated (RMRU) ages and speculative most recently updated (SMRU) ages respectively. The RAC also includes a data portion to store predicted subroutine addresses (PSRA).

Abstract: Part or all of an instruction decoder is constructed of a first reconfigurable circuit wherein a circuit structure thereof can be changed according to an external signal. Further, a second reconfigurable circuit which is connected to output side of a register file as part of processing unit and wherein a circuit structure thereof can be changed according to an external signal is preliminarily provided. For special use, to achieve a predetermined operating function, the second reconfigurable circuit is reconstructed by the external signal. Further, a particular instruction corresponding to the predetermined operating function is set, and the first reconfigurable circuit is so reconstructed by an external signal that when the particular instruction is inputted, a corresponding control signal is outputted.

Abstract: A printer that is instructed to perform a printing job analyzes the job and determines a process to be executed, and identifies the performances of the printer and other printers and their states. Based on the results of the analysis and on the states of the printers, the printer decides whether it should not perform a process or whether the process should be performed by another printer. It also decides whether a process is unnecessary or is not permitted for a user, and halts the performance of such a process. When it determines that a process should be performed by another printer, it transfers the job to that printer.

Abstract: The present invention is directed towards a means to detect and reorder out of order instructions that may violate data coherency. The invention comprises a mis-queue table for holding entries of instruction data, each entry corresponding to an instruction in a computer microprocesor. The instruction data in each entry comprises: i) address information for the instruction; ii) ordering information for the instruction, indicating the order of the instruction relative to other instructions in the mis-queue table; iii) data modification information for the instruction, for indicating a possibility of modified data; and iv) out of order information, for indicating that a newer instruction has completed before the corresponding older instruction to the entry. The invention also comprises an out of order comparator for comparing an address of a completed instruction to any address information entries in the miss queue.

Abstract: A data processing circuit is arranged to execute program instructions defining nested loops. A loop is defined in terms of a start address, an end address and a number of loop iterations. The processing circuit includes a program counter and a plurality of loop counting elements. Each of the loop counting elements includes a start address register, an end address register, a loop iteration register and means for comparing the value stored in the respective end address register with the output from the program counter.

Abstract: An apparatus and method for accelerating interpretive environments may burst-load selected blocks of instructions into a processor cache. In an illustrated example, an interpretive instruction set implementing a virtual machine is modified to include a jump instruction embedded in each interpretive instruction. Each of the jump instructions points to a successive interpreter instruction, and the last jump instruction is a return to the main program. The interpretive instructions are crafted to occupy a single cache line as a compiled, linked, and loaded image. Consequently, burst-loading is accomplished by pointing to the jump instruction within an initial interpretive instruction. The cache registers a miss when the processor attempts to load the jump instruction, and a MMU loads a main memory block containing the initial interpretive instruction into a cache line. The jump instruction is executed, which results in the MMU loading a successive interpreter instruction into a cache line.

Abstract: Variable-length instructions are prepared for simultaneous decoding and execution of a plurality of instructions in parallel by reading multiple variable-length instructions from an instruction source and determining the starting point of each instruction so that multiple instructions are presented to a decoder simultaneously for decoding in parallel. Immediately upon accessing the multiple variable-length instructions from an instruction memory, a predecoder derives predecode information for each byte of the variable-length instructions by determining an instruction length indication for that byte, assuming each byte to be an opcode byte since the actual opcode byte is not identified. The predecoder associates an instruction length to each instruction byte. The instructions and predecode information are applied to an instruction buffer circuit in a memory-aligned format.

Abstract: A load/store unit searches a store queue included therein for each byte accessed by the load independently from the other bytes, and determines the most recent store (in program order) to update that byte. Accordingly, even if one or more bytes accessed by the load are modified by one store while one or more other bytes accessed by the load are modified by another store, the forwarding mechanism may assemble the bytes accessed by the load. More particularly, load data may be forwarded accurately from an arbitrary number of stores. In other words, forwarding may occur up to N stores (where N is the number of bytes accessed by the load). In one particular embodiment, the load/store unit generates a bit vector from a predetermined set of least significant bits of the addresses of loads and stores. The bit vector includes a bit for each byte in a range defined by the number of least significant bits. The bit indicates whether or not the byte is updated (for store bit vectors) or accessed (for load bit vectors).

Abstract: Data communications apparatus is described comprising a general purpose computer and an adapter for enabling the computer to be connected to a data communications network. The computer and the adapter are interconnected by a data card interface. The general purpose computer comprises a first driver arranged to provide a first application program with a data transport connection to the data communications network via the data card interface using a serial COM port. A second driver is arranged to enable a second application program to communicate with the adapter simultaneously with said first application. The adapter is arranged to enable the second application program to make use of additional data services provided by said network via the second driver program. In this way, in addition to its serial communication channel an alternate communication channel is provided between the data card and the computer which allows other applications to make use of the additional data services provided by the network.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in the array is capable of performing a customized data selection and storage, instruction execution, and result destination selection, by uniquely interpreting a broadcast instruction by using the identity of the processor executing the instruction. In this manner, processing elements in a large multi-processing array can be dynamically reconfigured and have their operations customized for each processor using broadcast instructions.

Abstract: In executing a new method, a hardware processor loads the execution environment on a stack in the background and indicates what portion of the execution environment has been loaded so far, e.g., simple one bit scoreboarding. Thus, the hardware processor tracks the information in the execution environment loaded on the stack. The hardware processor tries to execute the bytecodes of the called method as soon as possible, even though the stack is not completely loaded. If accesses are made to variables already loaded, overlapping of execution with loading of the stack is achieved. Thus, execution and loading continue until information in the execution environment needed for the execution is not on said stack as indicated by said tracking.

Abstract: A millimode capable computer system provides control to millicode to allow the BHT operations to continue except when the these special situations occur that require control of instruction fetch operations must be provided and the BHT can be turned off for some sections of code execution, but not disabled for all. A single free running BHT functions for both a normal mode and a millimode for the central processor which can execute in millimode with a branch history table directing instruction fetch for which both a global BHT disable and millicode disables exist. Hit detection logic receives input from the global BHT disable, as well as from an initialized control register bit and a processor control register bit to select the correct set target information and generate a "branch history table hit detected" control signal.

Abstract: A pipelined multiprocessor system for ESA/390 operations which executes a simple instruction set in a hardware controlled execution unit and executes a complex instruction set in a milli-mode architected state with a millicode sequence of simple instructions in the hardware controlled execution unit, comprising a plurality of CPU processors each of which is part of said multiprocessing system and capable of generating and responding to a quiesce request, and controls for system operations which allow the CPUs in the ESA/390 system to process the local buffer update portion of IPTE and SSKE operations without waiting for all other processors to reach an interruptible point, and then to continue program execution with minor temporary restrictions on operations until the IPTE or SSKE operation is globally completed. In addition, Licensed Internal Code (LIC) sequences are defined which allow these IPTE and SSKE operations to co-exist with other operations which require conventional system quiescing (i.e.

Abstract: The present invention intends to provide an instruction prefetching apparatus capable of reducing a delay caused by branch prediction error by prefetching instruction based on a condition of a conditional branch instruction if the condition is already determined at the prefetching of the branch instruction. In the apparatus, a first decoding unit judges whether or not a processed instruction is a conditional branch instruction or not and whether or not the instruction is a condition generate instruction which determines branch condition. A condition determination signal generating means compares an address of a condition generate instruction with the content of a program counter to judge whether the condition is already determined or not, and according to the judgment, outputs a condition determination signal to a condition determination judging unit.

Abstract: The invention, in one embodiment, is a static instruction decoder including a plurality of instruction inputs, a circular instruction queue, and an instruction rotator. The circular instruction queue is capable of receiving instructions from the instruction inputs, statically decoding the received instructions, indicating how many of the decoded instructions may issue in a next clock cycle, and outputting the decoded instructions in the next clock cycle, the number of instructions output being the number indicated. The instruction rotator is indexed by the indication of the circular instruction queue and points to the first instruction to issue in the next clock cycle.

Abstract: Multi-way branching is implemented via a single instruction by providing a computer system with a hardware token-to-address table, loading the table with branch target data correlating to the multi-way branch instruction, including software for execution with at least one multi-way branch instruction executing that branch instruction by accessing the table. The computer system is conventionally supplied with branch logic and general purpose register stack with a multi-ported output interface. The hardware resource added implementing the multi-way branch operation includes the table in the form of addressable storage comprising a plurality of multi-byte locations with a write data input and a read data output. A decoder is connected between one port of the general purpose register interface with an output to select one of the multi-byte locations for an input or output operation. The write data input of the addressable storage or table is connected to another port of the general purpose register interface.

Abstract: A multiprocessor system comprising a core memory (RAM), processing units (CPU.sub.1 -CPU.sub.j), each being provided with a cache memory (MCj), a directory (RG.sub.j) and a management processor (PG.sub.j); the core memory (RAM) is connected to an assembly of shift registers (RDM.sub.1 -RDM.sub.j) in such a way as to permit, in one cycle of the memory, a parallel transfer by reading or writing of data blocks; each cache memory (MC.sub.j) is connected to a shift register (RDP.sub.j)in such a way as to permit a parallel transfer by reading or writing of data blocks. An assembly of series connections, (LS.sub.1 -LS.sub.n) is provided between the assembly of memory shift registers and the assembly of processor shift registers to permit the transfer of data blocks between each pair of associated registers (RDM.sub.j -RDP.sub.j); the addresses of the data blocks can be transmitted between processor (CPU.sub.j) and the core memory (RAM) either by the series connections or by a common address bus (BUS A).

Abstract: A system and method for register renaming and allocation in an out-of-order processing system which allows the use of a minimum number of physical registers is described. A link list allows concatenation of a physical register representing a certain instance of the corresponding logical register to the physical register representing the next instance of the same logical register. By adding and removing links in this link list, it is possible to manage the assignment of physical registers to logical registers dynamically. Both the physical registers representing speculative instances and the physical registers representing in-order instances are administrated together. This is done by means of an in-order list, which indicates the physical registers that actually represent the architected state of the machine.