Abstract: A trace memory in the emulator is formed into a plurality of memory banks. Data to be traced is in principle stored sequentially in each memory bank. A trace condition setting circuit (trace registers) and a trace condition agreement detecting circuit (comparators) are provided to generate a valid/invalid flag FB indicating whether or not the data meet the set condition. This flag FB is stored along with the trace data in each memory bank.

Abstract: A user controlled apparatus and corresponding method for accepting or rejecting a data packet which is being transferred between a client and server over a cable and a cable communication network. A memory system cooperates with a CPU and a cable modem to provide the desired results. The memory system includes applications programs, an applications interface layer, a communications protocol such as TCP/IP layer, a shim and a cable modem driver. The shim layer binds with the TCP/IP layer and the driver by exchanging pointers. The shim intercepts all data packet flow in both directions between the cable modem and the TCP/IP layer. Upon receipt by the shim of a packet received signal, logic intervenes. The logic decides to either pass the packet on or reject it based on the status of a listen flag which may be set by the client and/or the server.

Abstract: A floating point unit (60) capable of executing projection instructions provides performance improvement in multiple precision floating point arithmetic. The projection instructions provide for obtaining partial sequences of numbers, products, and sums which have definite alignments and widths which a programmer can set. This allows very fast computation of both individual intermediate computations and final results. A range projection instruction (210, 410) builds a mask with an exponent from one source (230, 430) and a mantissa from another (240, 440). A project instruction (610) builds a result by masking (660) mantissa bits in a source operand after alignment (630) with a mask. Projection multiply (810), add (1000), and subtract instructions build results by masking (850, 1070) mantissa bits of unrounded partial results after alignment (830, 1020, 1040) with a mask.

Abstract: A non-contact IC card includes a CPU for processing data, a memory for storing a program for controlling the CPU, an antenna for transmitting data and receiving data manner, a plurality of receivers each having a different signal detection level for detecting a signal received by the antenna, a selector for selecting one of the plurality of receivers and connecting it to the CPU, and a transmitter for transmitting a signal from the CPU through the antenna.

Abstract: A processing system includes a control flow monitor (CFM) checker for verifying a sequence of instructions performed by a pipelined processor (101). The CFM checker provides fail safe assurance against run-time errors in the sequence of instructions performed by a processor. The CFM checker verifies instruction sequence during run-time within 32 instruction cycles. The processing system provides an improved system and method having a CFM checker which minimizes wasted instruction cycles when performing branch instructions in a software program. Using a prefetch capability of an instruction pipeline and storing fixwords sequentially in memory, eliminates unnecessary instructions to fetch fixword values from external tables, thereby saving instructions and instruction cycles.

Abstract: In the case of constituting a processing unit having the characteristic of a VLIW type processing unit and the characteristic of a pipeline type processing unit, since reference to the result of operations is made among a plurality of processing units executing in parallel the operations, transfer of the register file is frequently generated among the processing units, resulting in insufficient effect of the high speed operations. In view of solving this problem, the predicate registers are provided and moreover a means for broadcasting the update data of the predicate register to all processing units is also provided. Thereby, operations for obtaining branching condition and numerical value can be realized in different processing units and the number of steps of the processing program can be reduced.

Abstract: A remote resource management system for managing resources in a symmetrical multiprocessing comprising a plurality of clusters of symmetric multiprocessors having interfaces between cluster nodes of the symmetric multiprocessor system. Each cluster of the system has a local interface and interface controller. There are one or more remote storage controllers each having its local interface controller, and a local-to-remote data bus. The remote resource manager manages the interface between two clusters of symmetric multiprocessors each of which clusters has a plurality of processors, a shared cache memory, a plurality of I/O adapters and a main memory accessible from the cluster. This remote resource manager manages resources with a remote storage controller to distribute work to a remote controller acting as an agent to perform a desired operation without requiring knowledge of a requester who initiated the work request.

Abstract: An initial waveform is defined as a set of amplitude values corresponding to a set of base positions. A series of waveform definitions is generated by incrementing or decrementing at least one amplitude value in the set of amplitude values according to a predetermined counting sequence and in dependence upon the current amplitude values. Waveform definitions are generated until an end condition is reached, such as a predetermined number of waveform definitions having been generated or a predetermined waveform definition having been generated. Waveform definitions can be stored in memory. A single waveform definition or the series of waveform definitions can be stored in memory. A single waveform or the series of waveforms can be plotted or displayed.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, th

Abstract: An object is to compatibly improve processing speed and storage capacity of semiconductor memory that the operation portion can use. Each of units (10a, 10b) each having an operation portion (11) and a memory portion (12) is formed of a single semiconductor chip. A data signal is separately stored in the two memory portions (12) in a bit-sliced form and each of the two operation portions (11) can use the 32-bit-wide data signal stored in the entirety of the two memory portions (12) through interconnections (22, 23). That is to say, each operation portion (11) can use a storage capacity twice larger than the capacity that can be ensured in a single semiconductor chip. Provided as interconnections for coupling the semiconductor chips are only the interconnections (22, 23) for transferring data signals from the two memory portions to the two operation portions (11).

Abstract: A computer for executing programs and having a structure for fetching instructions and/or operands along a path which may not be taken by a process being executed by a computer processor having a hierarchical memory structure with data being loaded into cache lines of a cache in the structure, and having block line fetch signal selection logic and computational logic with hedge selection logic for generating line fetch block signals for control of hedging by fetching instructions and/or operands along a path which may not be taken by a process being executed and making selected hedge fetches sensitive to whether the data is in the cache so as to gain the best performance advantage with a selected hedge fetch signal which accompanies each fetch request to the cache to identify whether a line should be loaded if it misses the cache to indicate a selected hedge fetch when this signal is ON, and rejecting a fetch request in the event the selected hedge fetch signal is turned ON if the data is not in the cache, th

Abstract: A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Abstract: The present invention discloses a method and system for observing and measuring in real-time an event inside a processor via an observation architecture (OA). The method comprises the steps of: (1) receiving a command instruction; the command instruction includes at least an opcode and an operand specifier; (2) decoding the command instruction by converting the opcode into control bits; (3) mapping the operand specifier to select at least one resource element of the observation architecture; and (4) capturing the event according to the control bits.

Abstract: A method and system for automatically stalling a pipeline of a processor to insure input/output (I/O) data integrity, where the processor has a write buffer and allows read instructions to bypass write instructions. Within the processor, write instructions are stored in a write buffer and read instructions are allowed, in certain circumstances, to bypass these stored write instructions. The present invention utilizes the operating system (OS) of a computer system to collect, in the page frame number (PFN) information, an indication as to whether or not a particular memory range is located in I/O memory space. The I/O memory space is defined as memory space that is used to communicate information to and from a peripheral device. When a memory address is placed into a translation lookaside buffer (TLB) of the processor, it is stored with the above indication. If this memory address is associated with a write instruction that becomes stored in the write buffer, the indication is copied into the write buffer.

Abstract: A Floating Point Unit (FPU) with a sixteen-bit fixed length instruction set for thirty-two bit data. The FPU operates as part of RISC microprocessor. The CPU does all memory addressing. Furthermore, data between the CPU and the FPU is transferred via a communication register. An FPU pipeline is synchronized with a CPU pipeline. The sixteen-bit fixed length instruction group has special instructions for immediate loading of a floating point zero and/or a floating point one. Two instructions are dedicated for this purpose. Furthermore, the 16-bit fixed length instruction group of the FPU flushes denormalized numbers to zero. The instruction set also rounds floating point numbers to zero. An FMAC instruction of the instruction set has the capability to accumulate into a different register for consecutive FMAC operations.

Abstract: A method and apparatus for providing predicated instructions in a processor employing out of order execution. In one embodiment, a plurality of decode units are configured to decode a plurality of variable byte length instructions and to provide a plurality of output of signals. The output signals are provided to a plurality of reservation stations coupled to the plurality of decode units within the superscalar microprocessor. Functional units are configured to receive the output signals from the plurality of decode units. The functional units include function execution units coupled to receive signals from the plurality of reservation stations and to provide a function output responsive to the output signals. The functional units further comprise a predication unit configured to determine whether a predetermined condition has occurred and either stop the function output or allow the function output to be transmitted depending on whether the predetermined condition has occurred.

Abstract: A system comprising a server having a memory, and a database defined in the memory; and a client in communication with the server, the server communicating to the client an interface for use in requesting a search of the database, and the server having virtual reality means for generating a virtual reality scene, the virtual reality scene varying depending on the results of the search.

Abstract: A system, apparatus and method which functions to restrain over-eager load boosting in an out-of-order processor through the implementation of a special "coloring" mechanism that colors dependent load and store instructions to ensure recognition of a dependency based on the assignment of a common multi-bit "color" scheme. In an exemplary embodiment, two bits of color are assigned to load and store instructions. These color bits are stored in a special array and are read when the load or store is read from the instruction cache ("I$"). The encoding of "00" for a load, for example, may indicate no coloring dependency for the load. Any encoding other than a "00" is utilized to indicate a store-load dependence for a store and load of the same color. The color bits for the load and store instructions are updated when a read-after-write ("RAW") hazard is detected by the memory disambiguation buffer ("MDB") for a store-load pair.

Abstract: Many users of handheld computer systems maintain databases on the handheld computer systems. To share the information, it is desirable to have a simple method of sharing the information with personal computer systems. An easy to use extendible file synchronization system is introduced for sharing information between a handheld computer system and a personal computer system. The synchronization system is activated by a single button press. The synchronization system proceeds to synchronize data for several different applications that run on the handheld computer system and the personal computer system. If the user gets a new application for the handheld computer system and the personal computer system, then a new library of code is added for synchronizing the databases associate with the new application. The synchronization system automatically recognizes the new library of code and uses it during the next synchronization.