Abstract: A system whereby a central processor continues operation beyond a serialization point before the architecture defines that it is permissible to do so. According to the system, it is ascertained whether correct results are being achieved after the serializing point. If some doubt develops about the correctness of the results, the processor is returned to its status at the serialization point and the processing is repeated. In one embodiment, correctness of results is determined by way of a monitoring mechanism which depends on the fact that interactions between CPUs are confined to references to storage. The operations which are performed prior to the time that the architecture allows them, are restricted to ones which depend on fetches made from storage.

Abstract: A multi-processor system and method arranged, in one embodiment, as an image and graphics processor. The multiprocessor system includes several individual processors all having communication links to several memories. Additional instruction memories are dedicated individually as cache memories to particular processors so that the processors can function in the multiple instruction, multiple data (MIMD) mode. When the processors function in the single instruction, multiple data mode (SIMD) the dedicated memories are reassigned for access by all of the processors for data. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

Abstract: A test circuit for testing a programmable array of a microprocessor including an instruction register for receiving an instruction signal from a data bus in response to a control signal and for outputting the received instruction signal to output lines, and a programmable logic array having a plurality of NAND circuits each forming a conductive path between first and second terminals when a predetermined instruction signal is received thereby from the register. Each of the NAND circuits includes a first terminal, a second terminal and a plurality of MOSFETs each having a first, a second and a gate electrode with the gate electrode coupled to an output line of the instruction register, and with the first and second electrodes being connected in series between the respective first and second terminals.

Abstract: The RAM includes sub-arrays having odd and even memory locations, respectively. A data move instruction results in externally generated row and column address signals which are decoded to cause a first memory location, in one of the sub-arrays, to be selected and data to be read. The next memory location in sequence, in the other of the sub-arrays, is then selected, without necessity for an additional set of row address signals, for writing of the read information. The row decoder includes row indexing circuitry actuatable upon receipt of a shift signal signifying that the first memory location is in the last column of a given row. When the shift signal is received, the write location is automatically selected to be in the succeeding row.

Abstract: An electronic key which includes a pseudo-random number generator. If the correct password is received, the contents of a secure memory will be outputted by the electronic key. However, if an incorrect password is received, that password will be used as a seed value for the pseudo-random number generator, and the resulting value will be outputted.Thus, if a copier exercises the key through all possible passwords, the incorrect passwords, as well as the correct password, will result in the same output data every time it is tried.

Abstract: An object based data processing system including an extensible set of object types and a corresponding set of "object managers" wherein each object manager is a program for operating with the data stored in a corresponding type of object. The object managers in general support at least a standard set of operations. Any program can effect performance of these standard operations on objects of any type by making an "invocation" request. In response to an invocation request, object management services (which are available to all object managers) identifies and invokes an object manager that is suitable for performing the requested operation on the specified type of data. A mechanism is provided for linking data from one object into another object. An object catalog includes both information about objects and about links between objects. Data interchange services are provided for communicating data between objects of different types, using a set of standard data interchange formats.

Abstract: Removal of invariant branches from nests of loops results in an optimized computer program with increased speed of execution. To accomplish this objective, each loop of a program is then examined, looking at inner loops before their containing outer loops, to locate conditional branch instructions which are loop invariant. Each conditional branch which is evaluated based upon loop invariant calculations is rewritten, outside the outermost loop for which this branch is invariant. The moved branch is modified to branch around the loop in which it was originally contained if its condition is evaluated false. A new copy of the loop is made in which the invariant branch is rewritten as an unconditional branch. In the original copy of the loop, the invariant branch is deleted, and a branch is inserted after the modified original loop to skip around the new copy when the original copy is executed.

Abstract: A microprocessor which includes means for detecting misaligned data reference is described. The detecting means is selectable such that when it is enabled and reference is made to a misaligned data object, a fault is produced which interrupts the currently executing program. The detecting means comprises two mode bits stored within the microprocessor. The first mode bit provides control of the fault at the least privileged level of execution (i.e., the applications level) while the second mode bit provides control of the fault at the most privileged level (i.e., the operating system level). Both mode bits must be set to "1" in order for the detecting means to be enabled. The use of two separate mode bits for optionally enabling alignment checking provides optimum programming flexibility.

Abstract: A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separate ports of each of the two memory modules. The three CPUs are loosely synchronized, as by detecting events such as memory references and stalling any CPU ahead of others until all execute the function simultaneously; interrupts can be synchronized by ensuring that all three CPUs implement the interrupt at the same point in their instruction stream. Memory references via the separate CPU-to-memory busses are voted at the three separate ports of each of the memory modules. I/O functions are implemented using two identical I/O busses, each of which is separately coupled to only one of the memory modules. A number of I/O processors are coupled to both I/O busses.

Abstract: A user interface, typically to an irrigation controller, prompts user responses by asking questions. The questions are hierarchally organized, preferably in a hierarchal tree having approximately three to six questions on each hierarchal level between root and leaves. All command and data input may be done with only an "OK" pushbutton switch, and with an additional ".uparw.", or ".dwnarw." pushbuttom switches. Each "OK" user response affirms the premise of a currently-displayed question, and advances the questioning to a related branch upon a next hierarchal level. The ".uparw." pushbutton is used to advance the questioning in a first direction. An optimal ".dwnarw.", or down arrow,pushbutton switch advances the presentation of successive questions in a second direction. An optional "HELP" switch invokes context-sensitive help messages.

Abstract: An integrated software architecture for a highly parallel multiprocessor system having multiple tightly-coupled processors that share a common memory efficiently controls the interface with and execution of programs on such a multiprocessor system. The software architecture combines a symmetrically integrated multithreaded operating system and an integrated parallel user environment. The operating system distributively implements an anarchy-based scheduling model for the scheduling of processes and resources by allowing each processor to access a single image of the operating system stored in the common memory that operates on a common set of operating system shared resources. The user environment provides a common visual representation for a plurality of program development tools that provide compilation, execution and debugging capabilities for multithreaded user programs and assumes parallelism as the standard mode of operation.

Abstract: A file management system allows the linking of objects. In each link one object serves as a parent and the other as a child. When a parent object is copied the parent object is copied to produce a copy of the parent object. Additionally, the child objects of the parent object are copied as well, except in the case when the child object is designated as a special public object, each child of the parent object is copied to produce a copy of the child object. Each copy of a child object is then linked to the copy of the parent object. When a child object is designated as a special public object, the child object is linked to the copy of the parent object.

Abstract: A method of programming a cache tag comparator by designing a semiconductor device's internal circuitry such that an input/output pin of the device may be programmed by an external resistor to ground that will indicate during the reset phase of the device that an alternate function for the pin is to be selected or that the pin itself is to be disabled.

Abstract: Disclosed is an electronic information retrieval apparatus in the apparatus when a retrieval instruction is supplied to the electronic information retrieval apparatus, broad sort names are read from storage (8) and are displayed on a CRT display. Within the displayed sort names, a desired one is designated by a keyboard (1), so that detailed sort names corresponding to the designated sort name are read from the storage (8) and are displayed on the CRT display (2). When an object detailed sort name is displayed and selected by the keyboard (1), corresponding picture information is displayed on the CRT display (2). This allows the user to efficiently retrieve stored information.

Abstract: According to a processing apparatus with a hierarchical structure, a machine instruction has a hierarchical structure of a task level operation code, a control structure level operation code, an arithmetic level operation code and a low order level operation code, and accordingly an operation object field has a hierarchical structure of task level data, control condition data, arithmetic object data and low order level data. In correspondence with the hierarchical structure of the instruction, the processing apparatus has a hierarchical structure of task level functional blocks, control structure level functional blocks, arithmetic level functional blocks and low order level functional blocks. The functional blocks respectively have instruction decoders which are operated with serial or parallel processing.

Abstract: An integrated circuit communication interface device includes data bus terminals, a serial output terminal, a serial input terminal, and an internal data bus. A data bus buffer connects the data bus terminals to the internal data bus. A transmit buffer connects the serial output terminal to the internal data bus. A receive buffer connects the serial input terminal to the internal data bus. Control circuitry controls the buffer so that the device receives or transmits data in either the Echoplex protocol or the RS 232 protocol. The device includes a data register which is programmed to select the device's mode of operation.

Abstract: A multi-dimensional processor cell and processor array with massively parallel input/output includes a processor array having a plurality of processor cells interconnected to form an N-dimensional array. The system includes a first group of processor cells having 2N dimensionally adjacent processor cells. At least one input/output device is connected to a surplus data signal port of a second group of processor cells each having fewer than 2N dimensionally adjacent processor cells, for providing massively parallel input/output between the multi-dimensional processor array and the input/output device. The processor system also includes a front end processor for providing processor array instructions in response to application programs running on the front end processor. A processor cell controller, responsive to the processor array commands, broadcasts a sequence of processor cell instructions to all of the processor cells of the multi-dimensional processor array.

Abstract: Apparatus for hot removal from/insertion to a connection bus of a non-removable-media magnetic recording unit, comprising a plurality of electromagnetic switches for isolation of the signal terminals of the unit from the bus, thereby preventing noise injection into the bus; control and timing circuits for deenergization of the unit only after opening of the switches and for enabling removal of the unit only after deenergization and circuits for imparting to the signal terminals of the unit a bias voltage intermediate or close to the electrical signal levels present on the bus, the insertion occurring by closing the switches when the unit is already powered and the terminals are biased so as to minimize the amplitude of the noise injected onto the bus.

Abstract: A node adapter chip for linking a node microprocessor to a serial data link incorporates a read/write circuit and an interrupt processing means to allow increased flexibility in connecting the adapter to different node microprocessors with different interface protocols. The read/write input circuit accepts dual strobe or single strobe type read/write commands and the interrupt processor accepts either conventional interrupt handling or "polled" operation for use with microprocessors that do not have interrupt capabilities. A flag multiplexer allows the controller in the node adapter to receive status information from a serial interface in the adapter without the need for extra data transfer cycles.

Abstract: An instruction decoder for a pipelined data processing unit simultaneously decodes two source specifiers and one destination specifier. All three of the specifiers can be register specifiers in which the specified operand is the content of a specified register. Any one of the specifiers can be a complex specifier designating an index register, a base register, and a displacement. Any one of the source specifiers can specify short literal data. Data for locating the two source operands and the destination operand are transmitted over parallel buses to an execution unit, so that most instructions are executed at a rate of one instruction per clock cycle. The complex specifier can have a variable length determined by its data type as well as its addressing mode. In particular, the complex specifier may specify a long length of extended immediate data that is received through the instruction buffer over a number of clock cycles.