Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

Abstract: A data-processing device has a clock generator for generating pulse signals .phi.1 and .phi.2, an ALU capable of executing various arithmetic-logic operations during cycles corresponding to the pulse signals .phi.1 and .phi.2,and a control unit for generating a control signal which causes the ALU to execute an arithmetic-logic operation according to an instruction. This data-processing device further includes a transfer switch for causing the ALU to execute an arithmetic-logic operation, which is for generating output data equal to input data, during a cycle in which the ALU would otherwise be idle.

Abstract: A computer system includes a condition register having multiple fields. Each field may be used as an independent condition register. A compiler which generates executable code for the computer system assigns instructions to different fields, allowing condition values to be saved while other conditions are evaluated and allowing consecutive instructions which generate or test condition values to be overlapped in their execution.

Abstract: A user interface, typically to an irrigation controller, prompts user responses by continuously autoscrolling questions. The questions are hierarchally organized, preferably in a hierarchal tree having approximately three to six questions on each hierarchal level between root and leaves. All command and data input may be done with only an OK/YES pushbutton switch, switches. Each OK/YES user response affirms the premise fo a currently-displayed question, and advances the autoscrolled questioning to a related branch upon a next hierarchal level. The NO pushbutton is never required to advance the questioning which is always autoscrolled, but instead serves, while depressed, to accelerate the autoscrolling of successive questions. A HELP response invokes context-sensitive help messages. A STOP response causes reversion in the hierarchy of questioning toward the root level, but does not stop the autoscrolling of questions.

Abstract: An application program includes an action processor which receives messages containing user syntactic actions. These actions are translated into semantic commands. The semantic commands are sent to a command processor for execution.The preferred embodiment of the computing system additionally includes an agent engine. The agent engine may be used to perform many functions. It may be used to receive semantic commands from an application, and to record the semantic commands for later playback. It may be used to send semantic commands from a task language file to an application program for execution by the command processor. It may be used to intercept semantic commands sent from action processor to the command processor. After the command is intercepted, the agent engine may be used to allow the semantic command to be executed, to prevent the semantic command from being executed.

Abstract: An information protective device protects stored information such as a program, data or the like in an information processing apparatus such as small type of portable computer or the like. The information protective device comprises a prohibition condition storing portion, which stores the writing prohibition condition to a storage unit for programs, data or the like, and a prohibition condition setting means, which carries out the writing of prohibition instructions to be stored in the storing portion to set the writing prohibition condition, so that the storage unit may be handled like so-called read only memory (ROM), whereby the storing contents may be protected more positively.

Abstract: A frame buffer memory controller allows rapid image updating while maintaining screen refresh data flow rate. One frame buffer memory controller controls one or more pixel depth columns comprising one or more frame buffer memory chips per pixel. Each frame buffer memory controller listens on a display processor bus for read, write or read-modify-write commands addressed to a pixel, or memory chip, under its control. Such commands, along with the associated addresses and data, are stored in a first-in, first-out (FIFO) buffer for execution during the first free memory cycle.

Abstract: A method and apparatus for providing program loop control in a data processor employs a special purpose instruction that substantially reduces the program overhead associated with conditional branching at the end of a program loop. The instruction first compares a loop counter with a decrement value. If the loop counter has counted down, a loop condition code, which is stored in a dedicated register bit, is cleared. Otherwise, the loop condition code remains set to indicate that further iterations of the loop are required. The decremented value of the loop counter is then stored in a loop counter register. In parallel with decrementing of the loop counter, a conditional branch is executed based on the value of the loop condition code set in the immediately previous iteration of the loop. If the loop condition code is cleared, i.e. if the loop has been completed, program control proceeds to the instruction following the loop after execution of the next instruction in sequence.

Abstract: A microcomputer having a memory which stores coded instructions. An instruction register coupled to the memory is used for temporarily storing instructions one byte at a time. A programmable logic array is coupled to the register and has a decoder which decodes the bytes of the instruction in the register to provide control signals, the bytes of each instruction temporarily stored in the register producing control signals during each of at least first and second successive machine cycles.

Abstract: A computer memory interpretation file, or structures file, enables automatic location and interpretation of memory resident components of operating system programs, user programs, data buffers, and the like. The structures file contains sufficient information pertaining to each control structure to allow a program using it to identify and locate each iteration of any component that may be memory resident. The structures file relieves the program of requiring reference definitions pertaining to the control structures or their sub-components and eliminates the requirement for programming logic normally necessary to recognize and perform specialized operations determined by the nature of the control structure being processed.

Abstract: A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags.

Abstract: The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to

Abstract: A protocol is disclosed for the round-robin distributed arbitration of access to a common resource, such as a bus, in a multiprocessor system or machine. The protocol assigns identity values to each agent, or processor, which are compared during each arbitration to determine which agent is awarded control of the bus. To enhance fairness agents having an identity value lower than the winner of the last arbitration are favored over agents having a higher identity value in the next subsequent arbitration.