Abstract: A circuit and method to force an output of a logic circuit to a known state when its supply voltage rises above a predetermined level includes an MOS logic transistor (122) connected between the supply voltage (129) and the output line (130) and connected to receive an input signal (126) on its gate. An MOS state controlling transistor (124) of opposite conductivity type from the MOS logic transistor (122) is connected between the output line (130) and a reference potential (-V.sub.ss), with its gate connected to the gate of the MOS logic transistor (122). A resistor (132) is connected between the supply voltage (128) and the gate of the MOS state controlling transistor (124). If the supply voltage (128) rises above the predetermined level established by the threshold voltage of the MOS state controlling transistor, the MOS state controlling transistor (124) conducts to produce the reference potential on the output line (130).

Abstract: A self-timed tri-state driver circuit for a dual-rail differential input and single-ended output is disclosed. The circuit generates a tri-state mode in response to an Output Enable (OE) input pulsing low. The OE signal input is driven high to place the driver circuit into a ready state. The circuit is maintained in a tri-state mode until data appears at the inputs. Once a data signal is received after the tri-state circuit is in the ready state, the output immediately outputs this signal. Therefore, the output of the driver is self-timed from the arrival of the data.

Abstract: A forward single-rail self-resetting reset circuit is utilized to reset a logic circuit to a selected state subsequent to each iteration of a logical operation on inputted data into the logic circuit. The reset circuit receives at least one of the data inputs and its complement signal so that the reset signal produced by the reset circuit is activated regardless of the voltage level of the data input signals.

Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: A NOR decode circuit which includes a latch composed of a pair of n-channel transistors and a pair of p-channel transistors with the p-channel transistor of one latch portion coupled to a reference circuit transistor via a first pass transistor and the p-channel transistor of the other latch portion coupled to the address select line controlled transistors via a second pass transistor. The pass transistors are also controlled by an enable row (ENROW) signal. The address transistors are larger and conduct more current than the reference transistor. When ENROW is activated, the n-channel transistors of the latch are enabled and current passes through one side of the latch circuit and through a third transistor in parallel with the address transistors if any of the address transistors are turned on. Current also flows through the other side of the latch circuit and through a fourth transistor in parallel with the reference transistor. The second pass transistor conducts a current I.sub.

Abstract: A data output buffer comprising a pull-up transistor having an N type-well, the pull-up transistor transferring a supply voltage from a supply voltage source to an output line in response to a logic state of data from an input line, a first PMOS transistor for switching the supply voltage from the supply voltage source to the N type-well of the pull-up transistor in response to a voltage on the output line, and a second PMOS transistor for feeding the voltage on the output line back to the N type-well of the pull-up transistor when the voltage on the output line is higher than the supply voltage from the supply voltage source. According to the present invention, the voltage on the output line can be prevented from being latched up to the supply voltage source when it is higher than the supply voltage from the supply voltage source. Therefore, the data output buffer has an enhanced operation speed and a minimized occupying area in a semiconductor integrated circuit device.

Abstract: A daisy chained clock distribution scheme for distributing a clock signal from a central communications clock driver to the nodes of a massively parallel multi-processor computer or supercomputer. The daisy chained clocking scheme is implemented using point-to-point clock distribution of a differential clock signal to the communication nodes of a plurality of processors in a multicomputer system or to components connected to a common bus in a high speed microprocessor system. Differential signaling is employed wherein the differentiality is maintained including through silicon. In an alternate embodiment, the clock pulse is also regenerated in each node component.

Abstract: A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e.g. one for an inverter and more for logic gates such as AND, OR, etc.) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively.

Abstract: A low power termination method and apparatus. The termination circuit is typically coupled to a bus through an interface node to receive a rising edge of an input voltage signal. A clamping device is coupled to the interface node and coupled to receive a clamping voltage, the clamping voltage being less than a termination voltage. The termination circuit also includes a bias supply providing a bias voltage. A control terminal of the clamping device is coupled receive the bias voltage, and clamps the interface node when the input voltage signal exceeds a termination voltage. A bias excursion of the bias voltage may be provided responsive to the rising edge so that the clamping device clamps the interface node before the input voltage signal exceeds the termination voltage. Similarly, a second clamping device biased by a second bias supply may be used. The second clamping device clamps the interface node after the input voltage signal falls below an expected low voltage.

Abstract: A voltage supply isolation buffer which prevents a voltage applied to an input or output of an IC device from reaching the power supply plane of the device. An inverter circuit is modified such that Vdd is coupled to the source of the p-channel pull-up transistor through a pn diode with the p terminal coupled to Vdd and the n terminal coupled to the source of the p-channel transistor. Under normal operation, Vdd forward biases the diode allowing a high voltage to be applied to the output of the inverter circuit when the p-channel transistor turns on. If, however, a voltage is applied to the output of the inverter circuit by an external voltage supply which is higher than Vdd, the diode will be reverse biased, preventing the voltage at the output node from raising the Vdd level.

Abstract: An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal.

Abstract: An all MOS single-ended to differential level converter including: first and second source follower circuits each including first and second PMOS semiconductors each having a drain, a source and a gate electrode; a current source commonly connected to the drain electrodes of the first and second PMOS semiconductors; an input circuit for providing to one of the gate electrodes a single-ended input signal and to the other an inverted single-ended input signal; and first and second load impedances connected to the source electrodes of the first and second PMOS semiconductors, respectively, for providing output analog differential signals at a level which is a function of the load impedances and current source magnitude.

Abstract: A field programmable gate array includes a logic blocks, switching elements for establishing a signal propagation path, and memory cells provided corresponding to the switching elements for storing data determining on and off states of corresponding switching elements. In this gate array, a supply voltage fed to a power input terminal is transmitted to power supply nodes of logic circuit blocks. A booster circuit boosts the supply voltage fed to the power input terminal and feeds the boosted voltage to power supply nodes of memory cells for programming a signal propagation path. A high-level signal potential of each memory cell is fed to the gate of an n-channel MOS transistor which functions as the switching element. The switching elements are disposed on signal lines and serve to interconnect the signal lines selectively to establish a signal propagation path.

Abstract: To minimize skew and jitter imposed upon signals communicated along a printed circuit signal path a termination circuit is formed proximate the sink or receiving element of the signals. The termination circuit can be resistive, coupling the signal path to a supply power and to a ground potential.

Abstract: A driver circuit has a single feedback transistor in the driver transistor well to provide a momentary feedback from source to gate and maintain conductance of the driver transistor during turnoff of the driver transistor and thus reduce ringing oscillation at the transistor source output. An enable/disable signal is applied to control conduction circuitry and the driver transistor and force the output to a high impedance state when the circuit is disabled. Clocked operation of the driver circuit is provided with circuitry merged with a latch. A terminal for receiving a global i.sub.dd test signal controls circuitry removing power to the driver circuit and applying a ground potential to the driver output in response to the global i.sub.dd test signal.

Abstract: There is provided a CMOS logic circuit designed in a manner to have preference to either operation speed or power consumption. This CMOS logic circuit comprises a first circuit assembly including a plurality of N number of P-channel type MOS transistors, a second circuit assembly including N-number of N-channel type MOS transistors, and a switching element operative so that ON/OFF state is switched by a clock signal inputted from the external. The first and second circuit assemblies and the switching element are connected in series, e.g., between power supply voltage terminal and the ground terminal.

Abstract: A programmable interface for selectively making connections between an output node of a logic module and an interconnection array in a field programmable gate array integrated circuit includes a first antifuse having a first electrode electrically connected to the output node and a second electrode connected to the first electrode of a second a second antifuse. The second electrode or the second antifuse is connected to the interconnection array. A high-voltage transistor, capable of withstanding programming voltages used in the integrated circuit to program the antifuses, is connected between the common connection comprising the second electrode of the first antifuse and the first electrode of the second antifuse and a fixed voltage potential such as ground. A control element of the high-voltage transistor is connected to circuitry for programming antifuses.

Abstract: A protection circuit for a semiconductor switch for switching a load is disclosed. Control circuitry is used for switching the semiconductor switch on in response to a switching signal and for switching the semiconductor switch off in response to a deactivation signal. A deactivation circuit is used for generating the deactivation signal. An overvoltage detector circuit responsive to a voltage at an output of the semiconductor switch that exceeds a predetermined value is used for generating an overvoltage signal. The overvoltage detector circuit includes a Zener diode that has its cathode coupled through a resistor to the output of the semiconductor switch and its anode coupled to the collector of the diode connected transistor. A first logic circuit is used for causing the deactivation circuit to generate the deactivation signal in response to the switching signal and the overvoltage signal.

Abstract: An electronically controllable low capacitance active bus line terminator achieves low output terminal capacitances by connecting emitters of switch transistors directly to the output terminals. Termination resistors are connected directly between an output of a voltage regulator circuit and collectors of the switch transistors. Emitters of optional clamp transistors can be connected to bases or collectors of the switch transistors to limit or prevent "ringing" of bus conductors connected to the output terminals if the switch transistors are turned on. The bus conductors are thereby isolated from parasitic capacitances associated with the termination resistors and the collectors of the switch transistors when they are turned off.

Abstract: An integrated circuit having system logic with programmable elements, decoding logic coupled to the programmable elements for addressing the programmable elements and a plurality of input/output buffer circuits for passing signals between the system logic and the exterior of the integrated circuit through input/output terminals is disclosed. Each input/output buffer circuit comprises an output driver stage having an output terminal connected to an input/output terminal; and a plurality of cells, each cell having a multiplexer, a flip-flop connected to an output terminal of the first multiplexer for storing a signal from the first multiplexer, a latch connected to an output terminal of the flip-flop for storing a signal from the flip-flop, and a second multiplexer connected to an output terminal of the latch.