Abstract: Bi-directional buffer circuit comprises a second P-channel transistor whose back gate is connected to a pad, a third P-channel transistor disposed between a gate of the second P-channel transistor and the pad with its back gate connected to the pad, and a first N-channel transistor and a fifth N-channel transistor whose gates are connected to a power source, so that an output buffer circuit, an input buffer circuit and a bi-directional buffer circuit can be produced without necessity of any additional processing step, wherein merely a single power source is incorporated, and a voltage higher than the source voltage is permitted to be applied to a common bus.

Abstract: An input buffer circuit for converting a TTL(TTL:Transistor transistor logic) level signal supplied from an outside into an internal CMOS level signal. The input buffer circuit comprises a power voltage terminal supplied with a power voltage, a power voltage sensing signal generator for detecting a level of the power voltage by inputting as source power the power voltage supplied to the power voltage terminal and for outputting a power voltage sensing signal respondent to the detected level, and switching means for convening an external signal into an internal signal and for performing an switching operation in response to a level of the power voltage sensing signal positioned on an output path to output the convened signal.

Abstract: A method and apparatus for providing active termination of a transmission line is accomplished by providing a pair of complementary transistors operably coupled to the transmission line, wherein one of the transistors provides the active termination impedance when the transmission line is in a first state, and the other transistor provides the active termination when the transistor is in a second state. The complementary pair of transistors may be gated such that when it is desired to remove the active termination from the circuit, it can be done. The line driver/receiver reduces part count by commonly using circuitry in the active termination stage and the receiver stage.

Abstract: A decoder circuit includes p-channel MOS transistors P.sub.1 and P.sub.2, n-channel MOS transistors N.sub.1 to N.sub.4 having gates to which data signals D.sub.1 to D.sub.4 are inputted, respectively, an n-channel MOS transistor N.sub.s connected in series to the n-channel MOS transistors N.sub.1 to N.sub.4 and having a gate to which the precharging signal .PHI. is inputted, and an n-channel MOS transistor N.sub.5 connected between P.sub.2 and N.sub.1. In the decoder circuit, the gate of N.sub.5 is connected to the drain of P.sub.2, and a capacity C.sub.H is connected between the gate of N.sub.5 and a power potential. In a holding state, the power potential is held by the aid of the capacity C.sub.H connected to the gate of N.sub.5.

Abstract: A voltage level shifter is disclosed having an input and an output. The input receives a first signal capable of fluctuating between at least two voltages. The voltage level shifter produces a second signal, at the output, based on the voltage of the input signal and two or more user-defined reference voltages.

Abstract: A bus termination method and apparatus, specifically, a terminator circuit, a driver/terminator circuit, and appropriate control logic. The terminator circuit and the driver/terminator circuit provide termination of an interface node to one of a first and a second voltage potential selected according to a previous logic value sampled on the input node at a time determined by a clock signal. The driver/terminator circuit also drives data values on the interface node. The terminator circuit and the driver/terminator circuit can be used in bus agents in a computer system. In one computer system configuration, a driving bus agent drives a signal line which is terminated by a predetermined terminating bus agent. Each bus agent compares its device identification to a bus master identification to determine whether to drive, terminate, or tristate the bus.

Abstract: A method of controlling termination of current driven circuits that bidirectionally transmit and receive a current driven signal, has the step of transmitting the current driven signal from a first one of the current driven circuits and receiving the signal by a second one of at least one of the current driven circuits while connecting only a termination circuit on the receiver side and disconnecting the other termination circuits. Therefore, the method of controlling termination of current driven circuits carries out simple termination switching control to prevent a decrease in the impedance of the output stage of the current driven circuit and transmit the current driven signal at correct amplitude.

Abstract: A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a "tree" configuration by providing a "push-pull" XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to "push" the output to a next stage.

Abstract: A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix.

Abstract: A controllable bus terminator for providing a switchable termination on a bus having a plurality of conductors, wherein the controllable bus terminator includes a voltage regulator, a plurality of termination networks, each having a first terminal and a second terminal wherein the second terminal of each of the termination networks provides an output terminal of the bus terminator. The bus terminator further includes a plurality of electrically controllable switches, each of the switches having a first port coupled to the voltage regulator and a second port coupled to the first terminal of a corresponding one of the termination networks wherein each of the switches couples the corresponding termination network to the voltage regulator when the corresponding switch is in a first state and wherein each of the switches disconnects the corresponding termination network from the voltage regulator when the corresponding switch is in a second state.

Abstract: An output buffer that controls the slew rate of its output signal is disclosed. The buffer includes a pull-up and a pull-down bipolar transistor coupled at a common output node in series between VDD and VSS. The buffer also includes a first set of parallel MOS devices coupled between the common output node and the base of the pull-down bipolar transistor. A second set of parallel MOS devices are coupled between the base of the pull-up output stage bipolar transistor and VDD. The gates of each set of MOS devices are coupled to a digital select signal. The amount of current driving the base of each of the pull-up and pull-down transistors (when they are enabled) is determined by the number of MOS devices enabled by the digital select signal. Thus, the buffer of the present invention is able to adjust the slew rate of its output signal to accommodate different loads coupled to the common output node.

Abstract: A low noise logic (LNL) family is disclosed. An inverter 10 has a pair of load devices NL1, NL2 coupled to the drains of NMOS transistors N 1, N2. The input signal is coupled to the gate of N 1. The drain of N 1 is coupled to the gate of N2. A constant current source 12 is coupled between V.sub.ss and the sources of the transistors N1,N2. Trickle current devices NTR1, NTR2 are coupled to the drains of N 1, N2, respectively to insure input control of the output states. A high logic signal on the gate of N1 steers the constant current to the load NL1 and turns NL2 off. A low logic signal on the gate of N1 turns N1 off and applies a high voltage to the gate of N2, turning N2 on. N2 steers the constant current to NL2.

Abstract: The invention employs an active element, a p-channel MOSFET, between a regulated voltage and a SCSI terminating line. An "ideal" current source terminator is most effective when a signal line is negated (low-to-high transition), whereas a resistive terminator is most effective when a signal line is asserted (high-to-low transition). The I-V characteristics of a p-channel MOSFET, wherein the relationship between the termination voltage and the termination current is characterized by a nonlinear and smooth voltage versus current curve, provide an optimized transient response for signal negations and signal assertions on a SCSI bus.

Abstract: In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programing circuits, and by adding a second fuse into each programing circuit; whereby, the bank of programming circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programming logic can set by alternately blowing one of its pair of fuses thus cutting off any current path through the programing circuit regardless of the programing state of the circuit.

Abstract: A first transistor is connected to a second transistor so that the first and second transistors may be initially biased in a non-conducting state when a first node is at a first voltage potential and a second node is at a second voltage potential. A potential altering circuit selectively alters the voltage potential at the first and second nodes, causes the first and second transistors to be in a conducting state for accelerating a voltage transistion at the first and second nodes toward final values, and maintains the first and second nodes at their final voltage potentials for implementing a desired Boolean function.

Abstract: An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

Abstract: A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . .

Abstract: Circuitry 10 is provided that contains two (or more) PLA matrix structures 12, 14 which share at least some outputs and are interconnected with a common output structure 18, individual input 30 and output 42, 62 structures, and an appropriate controller 28 for selecting which PLA matrix structure 12, 14 is to be employed. A common input structure 16 may be interconnected with the PLA matrix structures 12, 14 employed. The controller 28 may also be employed to power-down the PLA matrix structures not employed. The controller 28 may be static and select one matrix structure until reset, or dynamic and change as a function of some control signal.

Abstract: A memory includes a memory array and a decoder. The memory array includes a plurality of memory locations and the decoder is coupled to receive an address for decoding the address to generate a select signal for selecting one of the plurality of memory locations in the memory array for a memory operation. The memory further includes circuitry coupled to the decoder for delaying the select signal for a first predetermined delay time to generate a delayed select signal and for selectively applying one of the select signal and the delayed select signal to the memory array. The circuitry applies the delayed select signal to the memory array during the memory operation before the select signal is to be deasserted such that address hold time of the memory operation is decreased without affecting the memory operation.

Abstract: The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.