Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.

Abstract: A semiconductor device capable of realizing a synapse coupling of low power dissipation using a small number of elements and therefore a neuron computer chip of high integration degree and low power dissipation. The semiconductor includes a first gate electrode floating in potential formed on the region separating the source and drain regions through a first insulating film, a plurality of second gate electrodes capacitively coupled with the first gate through a second insulating film, and a first MOS type transistor, the source of which is connected to one of the second gates and the gate or the drain electrode is connected to a first interconnect for transferring signals of high or low potential level.

Abstract: A clock regulator that provides two controlled timing references per clock cycle on a single clock distribution. The regulator includes two phase detectors and phase aligner pairs to independently regulate both rising and falling edges of the clock distribution, rather than regulating only one edge as conventional regulators.

Abstract: A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal.

Abstract: A robust family of pre-conditioned complementary CMOS logic elements using scaled MOSFETs and a single clock phase which may be easily interconnected to form high speed logic networks. The family includes both N-type and P-type pre-conditioned logic elements using a skewed complementary CMOS structure to achieve low power and high speed. The logic elements achieve next generation CMOS performance yet are manufactured using present day processes and equipment. Logic element implementation is described in detail. A method for scaling the MOSFETs according to the present invention is provided, and several routing methods for reducing interconnection cross-talk are set forth.

Abstract: A semiconductor circuit or a MOS-DRAM wherein converting means is provided that converts substrate potential or body bias potential between two values for MOS-FETs in a logic circuit, memory cells, and operating circuit of the MOS-DRAM, thereby raising the threshold voltage of the MOS-FETs when in the standby state and lowering it when in active state. The converting means includes a level shift circuit and a switch circuit. The substrate potential or body bias potential is controlled only of the MOS-FETs which are nonconducting in the standby state; this configuration achieves a reduction in power consumption associated with the potential switching. Furthermore, in a structure where MOS-FETs of the same conductivity type are formed adjacent to each other, MOS-FETs of SOI structure are preferable for better results.

Abstract: A programmable logic array, where the programmable AND gate array in each block of macrocells conventionally generates a number of product terms to drive the macrocells in that block. Five product terms are assigned to each macrocell and are logically NORed together with two adjacent macrocell signals. The resultant signal drives the D terminal of the flip-flop in the macrocell. Independently, all five product terms are logically NORed together and the resultant signal is provided as an export signal to an adjacent macrocell for an additional product term use. Thirdly, each one of the product terms can be individually set as a separate private product term for use internally in that macrocell to replace the otherwise global provisions of internal macrocell signals such as set, reset, clock, output enable and inversion.

Abstract: A programmable two-line, two-phase logic array has a plurality of inputs, each having two input signals operating in two phases and memory cells provided at an intersection of the input signal lines and output lines corresponding to at least one function that cross the input lines. The memory cells are capable of being written in the fabrication process or by a field programming process that addresses the contact points at which the input and output lines cross. The two-line, two-phase logic circuit can be attained by the same technique as that used for attaining a conventional PLA without designing circuitry based on a conventional synchronous logic beforehand followed by replacing it with a two-line, two-phase circuit.

Abstract: A semiconductor device of this invention comprises on a substrate a first semiconductor region of one conductive type, first source and drain regions of the opposite conductive type formed in said semiconductor region, a first gate electrode formed in a region separating said source and drain regions, the first gate electrode being electrically floating through an insulating film, and at least two second gate electrodes connected to said first gate electrode by capacitive coupling, wherein an inversion layer is formed under said first gate electrode and said first source and drain regions are electrically connected together only when a predetermined threshold value is exceeded by the absolute value of a value obtained by linearly summing up the weighted voltages applied to said second gate electrodes.

Abstract: A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.

Abstract: An integrated circuit (IC) includes a device (10) that adapts the impedance to the characteristic impedance (Zc) of transmission lines (13) each connecting a transmitter (11) to a receiver (12). Two adaptation blocks (14, 15) reproduce the respective structures of the transmitters (11) and receivers (12) and their impedance is adapted by a reference resistor (Rr). A closed loop control device (Len, Lep, Lrn, Lrp) reproduces the adaptation conditions in the transmitters (11) and receivers (12) respectively.

Abstract: The present invention provides for an FPGA integrated circuit having an array of logic cells and interconnect lines interconnected by programmable switches, each formed from a nonvolatile memory cell. The logic cell is designed to provide logic or memory functions according to the setting of programmable switches within the cell. The logic cells in the array are interconnectable by a hierarchy of local, long and global wiring segments. The interconnections are made by the setting of programmable switches between the wiring segments.

Abstract: The NMOS and PMOS transistor both have a source and a floating gate. The source of the NMOS transistor is connected to both the source of the PMOS transistor and to an output termina. The floating gate of the NMOS transistor is connected to the floating gate of the PMOS transistor. A plurality of input gates are respectively capacitively coupled to the respective floating gates of the NMOS transistor and the PMOS transistor and are also respectively connected to a plurality of input terminals.

Abstract: A hysteresis circuit comprises a first logic section, a second logic section cascaded with the first logic section, and circuitry for controlling hysteresis threshold voltages of the hysteresis circuit. The hysteresis controlling circuitry conducts current from a source of a first supply voltage to the output lead of the first logic section during a low-to-high transition of an input voltage on an input terminal of the hysteresis circuit. The hysteresis controlling circuitry conducts current from the output lead of the first logic section to a source of a second supply voltage during a high-to-low transition of the input voltage on the input terminal of the hysteresis circuit. A clock generator integrated circuit chip employing the hysteresis circuit in a voltage controlled oscillator can generate squarewave signals of 150 MHz onto a plurality of output terminals when powered from approximately 3.3 volts throughout a 0 to 70 degree Celsius temperature range, a clock skew of less than 0.

Abstract: A SOI (Silicon On Insulator) logic circuit including serially connected power switching SOI MOSFETs (44, 45) and a logic circuit (43) constituted by SOI MOSFETs. The bodies of the MOSFETs of the logic circuit are made floating state, thereby implementing low threshold voltage MOSFETs. The bodies of the power switching MOSFETs are biased to power supply potentials, thereby implementing high threshold MOSFETs. The low threshold voltage MOSFETs enable the logic circuit to operate at a high speed in an active mode, and the high threshold voltage power switching MOSFETs can reduce the power dissipation in a sleep mode.

Abstract: Output logic macrocells for a programmable logic device (PLD) as well as a block clock/control circuit for use in the PLD to allocate multiple clock signals to each macrocell. Each macrocell includes a multiplexer selectively providing one of the multiple clock signals to a clock input of a storage element. The storage element additionally receives a sum of product terms output from an OR gate at its data input. The storage element is configured so that, depending on the clock input, it will function in a latch mode, a D-type flip-flop mode with either single edge or dual edge triggering, a combinatorial mode, a mixed clock mode, a reset mode, or a preset mode.

Abstract: In a level conversion circuit for converting a pair of first-level signals into a pair of second-level signals, an input buffer circuit converts the pair of first-level signals into a pair of buffered signals which vary within a first voltage range situated below a second voltage range within which the pair of first-level signals vary. An amplifier circuit, which includes a plurality of CMOS differential amplifier circuits cascaded, converts the pair of buffered signals into the pair of second-level signals varying within a third voltage range broader than the second voltage range of the pair of first-level signals.

Abstract: A system has the capability to determine the termination status of a data-communication bus therein. The system includes a source of a bus signal from a bus, a selectively activated current sink that communicates with the source of the bus signal, with a detection activation input, and a source of a detection signal in communication with the detection activation input of the current sink. There is a source of a first reference voltage, and a source of a second reference voltage, the second reference voltage being less than the first reference voltage. A high-termination comparator has an upper voltage input that communicates with the source of the bus signal, a lower voltage input that communicates with the source of the first reference voltage, and a logical high-termination output.

Abstract: A system in which line reflections in a clock distribution network are cancelled by providing the clock distribution network with a branching point and suitably arranging recipient devices with respect to the branching point to provide for clock pulse reflection cancellation and attenuation. Moreover, the system can be arranged so that clock pulse reflections are not received as pulses which are discrete from legitimate clock pulses. The system also provides capability for reducing electromagnetic interference.