Abstract: Method and apparatus for exploiting exclusivity of operation between a plurality of logic gates. The apparatus comprises a circuit having a plurality of logic gates. Each logic gate comprises a unique control input, and shares a data input with each of the plurality of logic gates. Control signals received at the control inputs insure exclusivity of operation between the logic gates. The shared data input is coupled to a shared fet which may serve as a virtual power supply for each of the plurality of logic gates.

Abstract: An FPGA architecture is provided which uses logic unit output lines of more than one length and provides extension lines to increase the reach of a logic unit output line. The architecture allows extremely fast connections between one logic unit and another. Also, all logic unit output lines drive about the same number of buffered programmable interconnection points (PIPs) so that the signal delay between one logic unit and the next can be predicted regardless of the functions and routing which have been selected by a user. The frequency of PIPs decreases as distance from the originating logic unit increases. This has the benefit of cooperating with software which tends to place interconnected logic in close proximity. The architecture is preferably implemented with a tile layout with one logic unit in each tile, and logic unit input and output lines extending through several tiles. Thus one tile boundary is like another and there is minimum hierarchy.

Abstract: The invention is a unique high speed Programmable Logic Device ("PLD") AND array with separate nonvolatile memory. The invention utilizes a separate nonvolatile memory to isolate the effect of nonvolatile transistors from the proper operation of the PLD AND array. The invention also results in a substantial increase in the amount of current flowing through transistors charging and discharging the PLD AND array bit lines. This in turn significantly increases the speed of the invention's PLD AND array. Moreover, the invention makes the current charging or discharging the PLD AND array bit lines more predictable. These advantages of the present invention are achieved by a nonvolatile memory that is separate from the AND array itself and also by utilizing NMOS transistors in the AND array instead of using the prior art nonvolatile transistors such as EEPROM transistors in the AND array.

Abstract: A clock signal providing circuit with enable and pulse generator with enable for use in a block clock circuit of a programmable logic device (PLD), the block clock circuit for allocating multiple clock signals to each macrocell of the PLD. The clock signal providing circuit includes circuitry which functions to change states in response to a pin clock signal when an enable signal is active, and to maintain its current state when the enable signal is inactive. The pulse generator includes circuitry which functions to provide a pulse at a first edge of a pin clock signal if an enable signal remains active from prior to receipt of the first edge of the pin clock signal.

Abstract: A field programmable gate array (FPGA) system for time multiplexing a plurality of programmable configurations of the FPGA. The system includes a plurality of configuration memory cells which are loaded with configuration information. A time slice selector couples selected configuration memory cells to programmable switch elements that determine the configuration and function of the logic within the FPGA. A time slice controller determines which of the configuration memory cells the time slice selector couples to the programmable switch elements. The configuration memory cells may be implemented with half SRAM cells and the time slice selector may be implemented with P-channel transistors.

Abstract: A programmable high speed routing switch is provided which has a lower ON-resistance so as to increase its gate oxide reliability. The routing switch includes a non-volatile memory cell (12) having a floating gate (FG). The floating gate is selectively charged and discharged to provide either a net positive potential or a net negative potential. The routing switch also includes a memory transistor (14), a pass gate transistor (16), and a poly load element (18). The source of the memory transistor is connected to a first power supply potential. The gate of the memory transistor is connected to the floating gate of the memory cell, and the drain thereof is connected to the gate of the pass gate transistor and to a first end of the poly load element. The drain of the pass gate transistor is connected to a first signal line (PG1) and the source of the pass gate transistor is connected to a second signal line (PG2). The second end of the poly load element is connected to a second power supply potential.

Abstract: A circuit and method for providing a bus switch that translates voltage from one level to a second, lower level. A FET bus switch transistor 310 is integrated on the same silicon chip 320 with one or more diodes 330 in series with Vcc, the power supply 340. A bias current source 350 is included to bias the diode. The diodes and current source are configured to provide additional voltage translation so that when a control input couples the input pin at the source of the FET bus switch to the output pin at the drain of the FET bus switch, the voltage at the output pin can be placed at a predetermined level. The bus switch thus acts as both a bus coupling device and a voltage translation device.

Abstract: Delay time characteristics of rise time and fall times of an output in a CMOS output buffer converting CMOS logic signals into ECL logic signals are made coincident with each other to eliminate various kinds of bias-voltage power supplies required for discharging the charge of capacitance parasitically present on an output-side. The amplifier 1 amplifies an input and supplies a driving input for an outputting P-channel MOSFET 2. A bypass control circuit 4, which inputs gate signals 1001 from the amplifier 1 and a drain potential of the outputting P-channel MOSFET 2 from an output terminal 105, acts as a NAND circuit of those two inputs, and feeds gate signals 1002 so as to cause conduction of the bypassing P-channel MOSFET only at a transient period during which a "high" level outputted to the output terminal 105 is converted into a "low" level, thus the charge on a load capacitance parasitically arisen on the output terminal 105 side is discharged.

Abstract: In the output buffer circuit, when an enable signal is inputted to deactivate the main buffer circuit (MB1) and further when a voltage higher than the first supply voltage V.sub.DD is applied to the output terminal (I/O), since the fifth P-type transistor (QP2) is turned on, the voltage at the output terminal is applied to the gate of the third P-type transistor (QP1), so that this transistor (QP1) is perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing from the output terminal (I/O) to the first supply voltage (V.sub.DD) terminal through the third P-type transistor (QP1). Further, since the sixth P-type transistor (QP4) is turned on, the voltage at the output terminal is applied to the gate of the second P-type transistor (QP6) through the sixth P-type transistor (QP4), so that this transistor (QP6) can be perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing to the first supply voltage (V.sub.

Abstract: A logic signal level translation method and apparatus having very low dropout with respect to the powering rails and having a tri-state mode of operation allowing the output terminal to be driven to voltages beyond the highest supply voltage coupled thereto without significant power dissipation within the circuit. The output circuit includes well or body snatching devices which are controlled to assure that the wells of the output devices are able to follow extremes in voltage of the output terminal without biasing to conduction a PN junction of one or more of the output devices. A preferred embodiment is disclosed.

Abstract: A field programmable gate array architecture comprises a plurality of horizontal and vertical routing channels each including a plurality of interconnect conductors. Some interconnect conductors are segmented by user-programmable interconnect elements, and some horizontal and vertical interconnect conductors are connectable by user-programmable interconnect elements located at selected intersections between them. An array of rows and columns of logic function modules each having at least one input and one output is superimposed on the routing channels. The inputs and outputs of the logic function modules are connectable to ones of the interconnect conductors in either or both of the horizontal and vertical routing channels. At least one column of random access memory blocks is disposed in the array.

Abstract: A CMOS inverter has two p-channel FETs connected in series between V.sub.DD and the inverter output node, an upper FET connected to V.sub.DD and a lower FET connected to the output node. The gate of a upper FET and the gate of the inverter n-channel FET are connected to the circuit input through a series FET that protects the gate oxide of these FETs by turning off if a high voltage appears at the circuit input. The circuit is useful as a buffer that receives binary voltages that may be higher than the binary voltages of the circuits of the same chip. The gate of the upper p-channel FET is connected to the input and turns off fully to block a leakage current that would otherwise flow when the n-channel FET is turned on but the lower p-channel FET is left partly conducting by the voltage drop across the series FET.

Abstract: A programmable logic device including a plurality of programmable atomic logic elements (PALEs) where each PALE has a plurality of data inputs and generates a data output signal. The PALEs are logically arranged as a plurality of hierarchically coupled partitions. Each partition is defined by a unique set of the next lower hierarchy partitions and an interconnect bus that extends only to the unique set of the next lower partitions that are within that partition. The lowest level of hierarchy is one of the plurality of PALEs. A plurality of hyperlinks provided within each PALE programmably couples the PALE data output signal to each of the interconnect busses in each of the higher levels of hierarchy that include the PALE. Preferably, the PALE also includes a tunnel connection for coupling the PALE data output signal to adjacent neighbor PALEs without using the interconnect bus of any of the partitions.

Abstract: An improved decoder with a reduced architecture that decodes a plurality of input signals that include a least significant input signal. The decoder comprises at least one pair of adjacent logic gates, each of the at least one pair of logic gates receiving at least one logic input signal that is selected from a group of logic signals that include the input signals to the decoder and the inverse of the input signals to the decoder. The logic input signals received by the at least one pair of adjacent logic gates are common to both adjacent logic gates of the pair, except for those logic signals representing the least significant decoder input signal and the inverse of the least significant decoder signal.

Abstract: In order to provide a high speed, stable and low voltage swing logic gate highly applicable to a low-cost BiCMOS process, a BiCMOS logic circuit of the disclosed invention has a pair of MOS transistors, the gates of which are supplied with complementary logic input signals, and the sources of which are coupled together and are supplied with a constant current. The constant current source used may include a bipolar transistor controlled by a reference voltage. Additionally, the constant current source may be a current mirror. The BiCMOS logic circuit of the disclosed invention has a complementary logic output signal. The voltage swing of the complementary logic output signal are determined by the reference voltage and resistance ratio of resistors in the circuit, so that the output voltage swing is independent of power supply fluctuation or temperature change.

Abstract: A wideband power driver having separate settings to delay a falling edge and rising edge of an output signal according to the present invention comprises an input node for receiving input signals and an output node for supplying output signals. A pulldown circuit is connected between the output node and a first supply voltage potential, the pulldown circuit having an input. A pullup circuit is connected between the output node and a second supply voltage potential, the pullup circuit having an input. A leakage current circuit is connected between the output node and the second supply voltage potential. A NOR gate has a first input, a second input connected to the input node, and an output. A first non-inverting delay element has an input connected to the output node and an output connected to the first input of said NOR gate.

Abstract: An off-chip driver circuit can operate in an output mode to drive a signal supplied at its input terminals to an output terminal. It can also operate in an input mode in which signals are driven from an external circuit via the output terminal onto the chip. In an output mode, the output terminal is clamped to reduce the effect of overshoot voltages, for example as a result of reflections from the external circuits.

Abstract: An electronic system includes a plurality of electronic circuits each having a signal input and output function, a bus to which the plurality of electronic circuits are connected, first termination resistors connected to ends of the bus, and a termination voltage circuit having a first part generating a first voltage and a second part generating a second voltage. The sum of the first voltage and the second voltage is supplied, as a power supply voltage, to output circuits of the plurality of electronic circuits connected to the bus. The second voltage is supplied to the first termination resistors as a termination voltage.

Abstract: An off-chip driver circuit having circuitry for providing protection against high voltages when the off-chip driver circuit is disabled is described. The circuitry for providing protection against high voltages utilizes a minimum number of transistors and therefore minimizes the chip area utilized by the off-chip driver circuit. An off-chip driver circuit has an input terminal and an output terminal. A pull-up transistor has a controllable path connected between a first power supply voltage and the output terminal of the off-chip driver circuit, and a control terminal connected to the input terminal via a pass gate connected to isolate the input terminal from high voltages applied to the output terminal. A control transistor has a controllable path connected between the control terminal of the pull-up transistor and the output terminal, and a control terminal connected to a control potential.

Abstract: A virtual high density architecture having shared memory cells for a programmable integrated circuit (IC) is provided. The architecture includes logic modules, a configuration memory unit (CMU), and a global interconnect memory (GIMU) unit. A logic cycle is divided into a number of time intervals. For each time interval, the CMU outputs information to configure the logic modules and the interconnect structure to realize an individual circuit stage of a circuit. Input and output data pertinent to this individual stage are retrieved from and stored in the GIMU based on addressing information generated from the CMU for each time interval. The CMU continuously reprograms the logic modules and interconnect structure for each time interval to realize different stages of the circuit while information used between stages is stored in the GIMU.