Abstract: A system to change a data window may include a plurality of registers. Each of the plurality of registers is operative, when activated, to receive data from a bi-directional data bus at a respective input. Each of the plurality of registers is activated in a predetermined sequence to latch a respective portion of the data from the bi-directional data bus so that each respective portion of the data has a longer data window at an output of each of the plurality of registers than at the respective input of each of the plurality of registers.

Abstract: Data not stored in the DRAM array of a SDRAM module is read from the SDRAM module in a synchronous data transfer. The data transfer, referred to as register read command/operation, resembles a read command/operation directed to data stored in the DRAM array in timing and operation. The register read command is distinguished by a unique encoding of the SDRAM control signals and bank address bits. In one embodiment, the register read command comprises the same control signal states as a MSR or EMSR command, with the bank address set to a unique value, such as 2'b10. The register read command may read only a single datum, or may utilize the address bus to address a plurality of data not stored in the DRAM array. The register read operation may be a burst read, and the burst length may be defined in a variety of ways.

Abstract: A semiconductor power device includes a device feature layer, a substrate contact layer and a voltage-sustaining layer between them. The voltage-sustaining layer includes alternating semiconductor and high permittivity dielectric regions, where each region extends from the device feature layer to the substrate contact layer. Due to the flux of charges transported dominantly through the dielectric regions, the whole voltage-sustaining layer behaves like a semiconductor having a much higher electric permittivity than that of the semiconductor itself, so that the field produced by the ionized impurities of the semiconductor regions can be much higher than that of the conventional one for sustaining the same reverse voltage, and the specific on-resistance can be lower than that of the conventional one. The use of high permittivity dielectric regions can also be applied to the charge-balance structure, i.e., to COOLMOST.

Abstract: A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selecting the page mode causes the device to output selected memory pages.

Abstract: Testing a TMR element includes a step of measuring initially a resistance value of the TMR element to provide the measured resistance value as a first resistance value, a step of measuring a resistance value of the TMR element after continuously feeding a current through the TMR element for a predetermined period of time, to provide the measured resistance value as a second resistance value, and a step of evaluating the TMR element depending upon a degree of change in resistance of the TMR element. The degree of change in resistance is determined based upon the first resistance value and the second resistance value.

Abstract: A hierarchical error correction system and method operable with a computer memory system. In one embodiment, the memory system comprises a plurality of memory modules organized as a number of error correction code (ECC) domains, wherein each ECC domain includes a set of memory modules, each memory module comprising a plurality of memory devices. A first error correction engine is provided for correcting device-level errors associated with a specific memory device and a second error correction engine for correcting errors at a memory module level, wherein the first and second error correction engines are operable in association with a memory controller operably coupled to the plurality of memory modules.

Abstract: A non-volatile semiconductor memory device includes a plurality of bit lines, a bit line contact corresponding to the bit lines, a first NAND string and a second NAND string, a first string selective transistor and a second string selective transistor, and a third string selective transistor and a fourth string selective transistor. The first and third string selective transistors are connected to each other, whereas the second and fourth string selective transistors are connected to each other. Each of the first and fourth string selective transistors has a first gate length and each of the second and third string selective transistors has a second gate length differing from the first gate length.

Abstract: Integrated semiconductor circuits, in particular, dynamic random access memories include a multiplicity of generator circuits for generating internal voltage levels from an externally applied supply voltage. During testing, the internal voltage levels are altered by the output voltage generated at the output of the generator circuit being adapted to an externally applied test voltage. If the test voltage is outside a tolerance range, the semiconductor circuit maybe destroyed. A protection circuit connected in parallel with the generator circuit limits the output voltage.

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

Abstract: In order to maintain the integrity of data stored in a flash memory that are susceptible to being disturbed by operations in adjacent regions of the memory, disturb events cause the data to be read, corrected and re-written before becoming so corrupted that valid data cannot be recovered. The sometimes conflicting needs to maintain data integrity and system performance are balanced by deferring execution of some of the corrective action when the memory system has other high priority operations to perform. In a memory system utilizing very large units of erase, the corrective process is executed in a manner that is consistent with efficiently rewriting an amount of data much less than the capacity of a unit of erase.

Abstract: Systems and methodologies are provided for activating a polymer memory cell(s) after production by subjecting the polymer memory cell to an electrical field, for an initialization thereof. Such initialization can facilitate the distribution and mobility of metal ions (or charged metallic molecules) within an active layer of the polymer memory cell. The memory cell can include various layers of alternating passive and active media, which are sandwiched between conducting electrode layers.

Abstract: Self-aligned split-gate NAND flash memory cell array and process of fabrication in which rows of self-aligned split-gate cells are formed between a bit line diffusion and a common source diffusion in the active area of a substrate. Each cell has control and floating gates which are stacked and self-aligned with each other, and erase and select gates which are split from and self-aligned with the stacked gates, with select gates at both ends of each row which partially overlap the bit line the source diffusions. The channel regions beneath the erase gates are heavily doped to reduce the resistance of the channel between the bit line and source diffusions, and the floating gates are surrounded by the other gates in a manner which provides significantly enhanced high voltage coupling to the floating gates from the other gates.

Abstract: A mask ROM includes bit lines, word lines intersecting with the bit lines and bit cells provided along the word lines, each of the bit lines being formed of a cell transistor having a gate connected to an associated one of the word lines. In the mask ROM, further provided is a source node commonly connected to respective sources of ones of the cell transistors having a gate connected to one of adjacent two word lines. A current flows from a selected bit line to a non-selected bit line via a cell transistor selected in reading out data and the source node.

Abstract: A method of managing power states of memory modules while performing memory access operations is discussed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state.

Abstract: When programming a contiguous page of memory storage units, every time a memory storage unit has reached its targeted state and is program-inhibited or locked out from further programming, it creates a perturbation on an adjacent memory storage unit still under programming. The present invention provides as part of a programming circuit and method in which an offset to the perturbation is added to the adjacent memory storage unit still under programming. The offset is added as voltage offset to a bit line of a storage unit under programming. The voltage offset is a predetermined function of whether none or one or both of its neighbors are in a mode that creates perturbation, such as in a program inhibit mode. In this way, an error inherent in programming in parallel high-density memory storage units is eliminated or minimized.

Abstract: In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.

Abstract: A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.

Abstract: A system and method of providing a voltage to a non-volatile memory. The system includes an output pin to provide an output voltage to a non-volatile memory and includes a memory to store a table. The table includes a plurality of operating voltage levels. The system further includes a voltage mode module to apply a first voltage at a first of the plurality of operating voltage levels at the output pin prior to a read operation on the non-volatile memory. The voltage mode module applies a second voltage at a second of the plurality of voltage levels at the output pin in response to a read operation that returns a failure condition.

Abstract: Methods and apparatuses prevent overtunneling in nonvolatile floating gate memory (NVM) cells. An individual cell includes a circuit with a transistor that has a floating gate that stores charge, and a capacitor structure for extracting charge from the gate, such as by tunneling. A counteracting circuit prevents extracting charge from the floating gate beyond a threshold, therefore preventing overtunneling or correcting for it. In one embodiment, the counteracting circuit supplies electrons to the floating gate, to compensate for tunneling beyond a point. In another embodiment, the counteracting circuit includes a switch, and a sensor to trigger the switch when the appropriate threshold is reached. The switch may be arranged in any number of suitable ways, such as to prevent a high voltage from being applied to the capacitor structure, or to prevent a power supply from being applied to a terminal of the transistor or to a well of the transistor.

Abstract: One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.