Abstract: During writing of fail addresses to address registers, when writing of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, or when a storage process of a number of fail addresses that is greater than the number of antifuses that have been provided in advance is about to be executed, delivering as output an overflow signal indicating that the writing or storage operation cannot be executed and reporting to the outside that remedy of defects by antifuses is no longer possible.

Abstract: A magnetic random access memory (MRAM) is compensated for write current shunting by varying the bit size of each MRAM cell with position along the write line. The MRAM includes a plurality of magnetic tunnel junction memory cells arranged in an array of columns and rows. The width of each memory cell increases along a write line to compensate for write current shunting.

Abstract: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Abstract: A ternary content addressable memory (TCAM) device comprising a plurality of TCAM cells for storing data, each TCAM cell having two memory cells and a comparison circuit for comparing between data stored in the memory cells and data input on a search line pair connected to the comparison circuit, wherein the comparison circuit comprises a first plurality of MOS transistors connected between a match line and a second plurality of MOS transistors, the second plurality of MOS transistors being connected to ground, wherein the first plurality of MOS transistors are gated by signals from the memory cells connected thereto and the second plurality of transistors are gated by signals from a search line pair. The TCAM device includes redundant memory cells which replaces by corresponding column memory cells determined to be defective. Each line of a search line pair is connected to a defective cell is discharged to ground.

Abstract: For one or more disclosed embodiments, a plurality of rows of memory cells in a memory bank are activated, and a column of memory cells in the memory bank is selected to select memory cells common to activated rows and the selected column. At least one of the selected memory cells common to activated rows and the selected column is selectively accessed. The selecting and the selectively accessing are repeated to access memory cells common to activated rows and a plurality of selected columns.

Abstract: A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.

Abstract: Integrated circuit antifuse circuitry is provided. A metal-oxide-semiconductor (MOS) antifuse transistor serves as an electrically-programmable antifuse. In its unprogrammed state, the antifuse transistor is off and has a relatively high resistance. During programming, the antifuse transistor is turned on which melts the underlying silicon and causes a permanent reduction in the transistor's resistance. A sensing circuit monitors the resistance of the antifuse transistor and supplies a high or low output signal accordingly. The antifuse transistor may be turned on during programming by raising the voltage at its substrate relative to its source. The substrate may be connected to ground through a resistor. The substrate may be biased by causing current to flow through the resistor. Current may be made to flow through the resistor by inducing avalanche breakdown of the drain-substrate junction or by producing Zener breakdown of external Zener diode circuitry connected to the resistor.

Abstract: A data output controller of a high-speed memory device and a method therefore. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external clock signal, a second section for analyzing data in an information storage unit, in which an internal timing is defined, by using values detected by the first section, and a third section for adjusting a data output timing in accordance with predetermined CAS latency based on analyzed values obtained through the second section. The data output controller to indicate an optimal point of a data output indicated by CAS latency information.

Abstract: A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to switch between two different input signals and two different clock signals and the use of an S-R flip-flop unit to output either the first input signal or the second input signal during different specified periods. This feature allows the architecture of the proposed multiple-clock controlled logic signal generating circuit to be more simplified than prior art and thus easier to implement.

Abstract: A light-emitting diode has a sub-mount, a first conductivity type substrate deposed on the sub-mount, a reflector layer deposed between the sub-mount and the first conductivity type substrate, a first conductivity type buffer layer deposed on the first conductivity type substrate, a first conductivity type distributed Bragg reflector (DBR) layer deposed on the first conductivity type buffer layer, an illuminant epitaxial structure deposed on the first conductivity type distributed Bragg reflector layer, and a second conductivity type window layer deposed on the illuminant epitaxial structure.

Abstract: A method and apparatus is provided for implementing a refresh rate control scheme that is capable of compensating for external factors. Using a circuit, a change in a current leakage relating to at least a portion of a memory device is detected. Furthermore, a refresh rate associated with the portion of the memory device is adjusted in response to detecting the current leakage.

Abstract: A semiconductor memory device precisely measures the offset voltage of a bit line sense amplifier. The semiconductor memory device of the invention includes: a bit line sense amplifier for amplifying a voltage difference between a bit line and an inversion bit line, which carry data written on a memory cell when the data is read; a data input/output line and an inversion data input/output line within a core region coupled to the bit line and the inversion bit line via one or more switches; a first external voltage supply pad connected to the data input/output line; a second external voltage supply pad connected to the inversion data input/output line; and an external voltage supply controller for switching a connection of the data input/output line and the first external voltage supply pad and a connection of the inversion data input/output line and the second external voltage supply pad.

Abstract: Programmable logic devices may use shadow memory for gathering diagnostic information while testing memory blocks. Memory block testing may be performed at any clock speed allowed during normal operation in a system such as the highest allowed clock speed. Built in self test circuitry and address and data paths are formed by loading configuration data into a programmable logic device. During write operations on a memory block under test, test data words are written into the memory block. A comparator compares data words read from the memory block to expected data words received from the test pattern generator to produce corresponding comparison data words. The comparison data words are written into the shadow memory. The same addresses are applied to the memory block under test and the shadow memory, so the stored comparison data words form a test results bit map indicative of errors in the memory block.

Abstract: A method of performing a self refresh of memory cells in a memory device. The memory device includes a first group of cell blocks and a second group of cell blocks and each cell block of the first group shares at least one sense amplifier with a cell block of the second group. The method includes simultaneously activating each cell block of the first group. While the cell blocks of the first group are activated, each memory cell in the first group is refreshed. The method further includes simultaneously activating each cell block of the second group. While the cell blocks of the second group are activated each memory cell in the second group is refreshed.

Abstract: It is made possible to provide a highly reliable magnetoresistive effect element and magnetic memory that operate with low power consumption and low current writing. The magnetoresistive effect element includes: a magnetization free layer including at least two magnetic layers subject to antiferromagnetic coupling and a non-magnetic layer provided between the magnetic layers; a tunnel barrier layer provided on one surface of the magnetization free layer; a first magnetization pinned layer provided on an opposite surface of the tunnel barrier layer from the magnetization free layer; a non-magnetic metal layer provided on an opposite surface of the magnetization free layer from the tunnel barrier layer; and a second magnetization pinned layer provided on an opposite surface of the non-magnetic metal layer from the magnetization free layer. The first and second magnetization pinned layers are substantially the same in magnetization direction. The non-magnetic metal layer includes Cu, Ag, Au, or an alloy of them.

Abstract: Data verification methods and/or nonvolatile memory devices are provided that concurrently detect data for a selected memory cell of the nonvolatile memory device and verify a programmed or erase state of previously detected data of a different memory cell of the nonvolatile memory device. Concurrently detecting data and verifying a programmed or erase state may be provided by a sense amplifier configured to sense data from a memory cell of the nonvolatile memory device, a latch configured to store the data sensed by the sense amplifier, an I/O buffer configured to store the data stored in the latch and a program/erase verifier circuit configured to control the sense amplifier, latch and I/O buffer to provided previously sensed data for a first memory cell to the program erase/verifier circuit for verification while the sense amplifier is sensing data for a second memory cell.

Abstract: A vertical insulated gate transistor is manufactured by providing a trench (26) extending through a source layer (8) and a channel layer (6) towards a drain layer (2). A spacer etch is used to form gate portions (20) along the trench side walls, a dielectric material (30) is filled into the trench between the sidewalls gate portions (20), and a gate electrical connection layer (30) is formed at the top of the trench electrically connecting the gate portions (20) across the trench.

Abstract: To store information in a ferroelectric material, a sample probe is used to bring about mechanical action on individual domains and thereby to cause a reversal of polarization in the individual domains, with electrodes situated below the ferroelectric material being able to have a bias applied to them to stabilize the change/reversal of polarization. The reversal of polarization causes an alteration in the surface topography of the ferroelectric material, and this alteration can be used to read the information. The stored information is therefore obtained by ascertaining the surface topography of the ferroelectric material. The information is written and read using an AFM tip, with the tip being able to be operated in contact or tapping mode for the purpose of writing, and additionally in noncontact mode for the purpose of reading.

Abstract: A memory device is disclosed that has a longer read time than write time and implements a parallel-read operation. The parallel-read operation saves reading time and thus accelerates a write operation that comprises a step of comparing incoming data with memory data that were stored in the memory before. The arrangement is especially applicable to an MRAM memory with 0T1MTJ memory cells. The parallel-read operation involves reading in parallel a large amount of data or all data to be compared from the memory into a first temporary memory. The write data is stored in a second temporary memory. The memory data contained in the first temporary memory is compared with the corresponding write data contained in the second temporary memory and allocated to the same address information. Only that write data is written to the memory, which is different from the corresponding memory data.

Abstract: A circuit is proposed which has a memory to which input data can be written at different write addresses with a first clock rate and from which output data can be read at different read addresses with a second clock rate. The memory can be fed a write reset pulse that resets the write address to an initial value. In addition, the memory can be fed a read reset pulse by means of which the data are output in a fixed temporal relationship. Finally, the circuit proposed is provided with switching means in order to derive the read reset pulse from the write reset pulse. This ensures that the two reset pulses cannot occur simultaneously.