Abstract: A pixel structure for use in a display panel includes a switching element and a storage capacitor. The switching element has a drain electrode and a source electrode disposed on a high-k dielectric layer with k being equal to or higher than 8. The storage capacitor has a first capacitor electrode, a second capacitor electrode and a third capacitor electrode, wherein a passivation layer is disposed between the second an third capacitor electrodes and the high-k dielectric layer is also disposed between the first and second capacitor electrodes. The pixel structure also has a common line connected to the first capacitor electrode, a source line, and a gate line arranged such that the source line, the gate line and the common line may cross over each other over a low-k dielectric layer at a cross-over area where k is equal to or lower than 5.

Abstract: In interconnect fabrication (e.g. a damascene process), a conductive layer is formed over a substrate with holes, and is polished to provide interconnect features in the holes. To prevent erosion/dishing of the conductive layer at the holes, the conductive layer is covered by a sacrificial layer (possibly conformal) before polishing; then both layers are polished. Initially, before polishing, the conductive layer and the sacrificial layer are recessed over the holes, but the sacrificial layer is polished at a lower rate to result in a protrusion of the conductive layer at a location of each hole. The polishing can continue to remove the protrusions and provide a planar surface.

Abstract: A method for using an offset vector tile gather to image a subsurface defines an offset vector tile gather by selecting a plurality of seismic traces from recorded seismic data. Each seismic trace in the offset vector tile includes reflections from subsurface reflectors and reflection points at depths below the surface of the subsurface. Each reflection point is in a given seismic trace, and each given seismic trace extends from a seismic source to a seismic receiver. The reflection points define an offset vector tile having a source line span and a receiver line span. The source line span is equal to or greater than a distance between adjacent seismic receiver lines, and the receiver line span is less than a distance between adjacent seismic source lines. The offset vector tile gather is used to produce a three dimensional image of the subsurface.

Abstract: A semiconductor device includes a pad disposed on a semiconductor layer, an insulating layer disposed between the semiconductor layer and the pad, a through-via penetrating the semiconductor layer and the insulating layer so as to be connected to the pad, and an isolation layer penetrating the semiconductor layer and surrounding the pad when viewed from a plan view.

Abstract: A method for operating a smart tool monitoring system is described. The method includes monitoring, by a controller within a smart tool monitoring system, a first parameter associated with a first component internal to the smart tool monitoring system. The method also includes determining, by the controller, whether the first parameter satisfies a first criterion. The method also includes performing a first action in response to a determination that the first parameter satisfies the first criterion. The method also includes receiving a measurement value from a sensor of an article of manufacturing equipment that includes a second component external to the smart tool monitoring system. The method also includes determining, by the controller, whether the measurement value satisfies a second criterion. The method also includes performing a second action in response to a determination that the measurement value satisfies the second criterion.

Abstract: A semiconductor device which can reduce power consumption and a method for manufacturing the same are provided. A semiconductor device comprises an Si (silicon) substrate, an SiC (silicon carbide) layer formed on the surface of the Si substrate, an AlN (aluminum nitride) layer formed on the surface of the SiC layer, an n-type GaN (gallium nitride) layer formed on the surface of the AlN layer, a first electrode formed at the surface side of the GaN layer, and a second electrode formed at the reverse face side of the Si substrate 1. The magnitude of electrical current which flows between the first electrode and the second electrode depends on electrical voltage between the first electrode and the second electrode.

Abstract: A turbomachine complex includes at least one motor-generator, at least one power source coupled to the at least one motor-generator, and at least one load dissipative device coupled to the at least one motor-generator. The turbomachine complex is configured to energize the at least one motor-generator through the at least one power source. The turbomachine complex is further configured to simultaneously energize the at least one at least one load dissipative device through the at least one motor-generator.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, an IC, a plurality of leads and a molding encapsulation. The first MOSFET is attached to the first die paddle. The second MOSFET is attached to the second die paddle. The third MOSFET is attached to the third die paddle. The fourth, fifth and sixth MOSFETs are attached to the fourth die paddle. The IC is attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the IC. The IPM is a small-outline package. It reduces system design time and improves reliability. The IC includes boost diodes. It reduces a package size of the IPM.

Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.

Abstract: A method for forming a semiconductor device includes forming a strained fin on a substrate, a sacrificial gate on a channel region of the fin, a first spacer adjacent to a sidewall of the fin, and a second spacer adjacent to the first spacer. A source/drain region is grown on an exposed portion of the fin. Atoms are driven from the source/drain region into the fin and form an oxide layer on the source/drain region. The second spacer and the oxide layer are removed. An insulator layer is formed over the source/drain region, and the sacrificial gate is removed to expose the channel region of the fin. A gate stack is formed over the channel region of the fin.

Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.

Abstract: A method for forming a semiconductor device includes forming a semiconductor fin over a surface of a substrate and forming sacrificial spacers on first and second sides of the semiconductor fin. The first side opposes the second side. The method includes recessing the surface to expose second and third surfaces, recessing the second surface to form a first cavity between the sacrificial spacers and the substrate on the first side, and recessing the third surface to form a second cavity between the sacrificial spacers and the substrate on the second side. The method includes forming a first bottom spacer in the first cavity and forming a second bottom spacer in the second cavity. A thickness of the first bottom spacer in a direction between the sacrificial spacers and the substrate is substantially equal to a thickness of the second bottom spacer in the same direction.

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Abstract: A light emitting device includes a package having a recess which includes a bottom surface and an inner peripheral surface around a periphery of the bottom surface. The package includes a first lead to define a first part of the bottom surface, a second lead to define a second part of the bottom surface, and a resin body to provide the inner peripheral surface and a remaining part of the bottom surface. The bottom surface includes a light emitting element mounting region in the first part and a groove surrounding the light emitting element mounting region. A light emitting element is mounted on the light emitting element mounting region. A light-transmissive resin is provided in the recess to be in at least a part of a groove surface. A light reflecting resin is provided between the inner peripheral surface of the recess and the light-transmissive resin.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth metal-oxide-semiconductor field-effect transistors (MOSFETs), a tie bar, a metal slug, a plurality of spacers, a plurality of leads and a molding encapsulation. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar and the plurality of spacers. A bottom surface of the metal slug is exposed from the molding encapsulation. A process for fabricating the IPM comprises preparing the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth MOSFETs, the tie bar, the plurality of leads, the metal slug and the plurality of spacers and applying a molding process to form the molding encapsulation.

Abstract: In fully depleted SOI transistors, specifically designed semiconductor materials may be provided for different types of transistors, thereby, for instance, enabling a reduction of hot carrier injection in transistors that are required to be operated at a moderately high operating voltage. To this end, well-controllable epitaxial growth techniques may be applied selectively for one type of transistor, while not unduly affecting the adjustment of material characteristics of a different type of transistor.

Abstract: An apparatus for generating an identification key is provided. The apparatus may include a first conductive layer formed on a semiconductor chip, a second conductive layer formed on the semiconductor chip, wherein a spacing between the first conductive layer and the second conductive layer is equal to or greater than a first threshold and equal to or less than a second threshold, and a reader configured to determine whether a first node associated with the first conductive layer and a second node associated with the second conductive layer are shorted, and to provide an identification key.

Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

Abstract: A vertical flash memory includes a plurality of vertical memory cells, wherein each of the vertical memory cells includes a selective gate, a main gate, a dielectric interlayer and a vertical channel layer. The selective gate is disposed on a substrate. The main gate is stacked on the selective gate. The dielectric interlayer isolates the main gate from the selective gate. The vertical channel layer is disposed on sidewalls of the selective gate and the main gate. The present invention also provides a method of forming said vertical flash memory.

Abstract: Methods for fabricating semiconductor devices may provide enhanced performance and reliability by recovering quality of a low-k insulating film damaged by a plasma process. A method may include forming a first interlayer insulating film having a trench therein on a substrate, filling at least a portion of the trench with a metal wiring region, exposing a surface of the metal wiring region and a surface of the first interlayer insulating film to a plasma in a first surface treatment process, then exposing the surface of the first interlayer insulating film to a recovery gas containing a methyl group (—CH3) in a second surface treatment process, and then forming an etch stop layer on the metal wiring region and the first interlayer insulating film.