Abstract: The method of validating a calibration of a phased-array inspection instrument uses a calibration block having two reflectors located below an inspection surface at two different depths.

Abstract: Various arrangements are provided related to thermal energy coordination systems. A thermal energy coordination system may analyze solar irradiance measurements to identify an overgeneration solar energy event. The system may activate a thermal energy storage event to coincide with the overgeneration solar energy event at the plurality of solar panels. The system, which can include many network-enabled smart thermostats, may control air conditioners or other HVAC system within various structures. The system may determine a time to initiate cooling and a temperature to which to cool the structure based upon the received indication of the thermal energy storage event.

Abstract: A method of manufacturing a nitride semiconductor substrate includes providing a silicon substrate having a first surface and a second surface opposing each other, growing a nitride template on the first surface of the silicon substrate in a first growth chamber, in which a silicon compound layer is formed on the second surface of the silicon substrate in a growth process of the nitride template, removing the silicon compound layer from the second surface of the silicon substrate, growing a group III nitride single crystal on the nitride template in a second growth chamber, and removing the silicon substrate from the second growth chamber.

Abstract: A method of manufacturing an OLED display is disclosed. In one aspect, the method includes providing a donor substrate including a material formed on one surface thereof and heating the material so as to form a barrier thin-film on the donor substrate. The method also includes providing an acceptor substrate and a substrate attached to the acceptor substrate, forming an OLED unit over the substrate, bonding the OLED unit and the barrier thin-film together, and irradiating a laser beam on the barrier thin-film so as to delaminate the donor substrate from the barrier thin-film.

Abstract: The present disclosure relates to a method for manufacturing a self-assembled nano-scale LED electrode assembly and more particularly, to a method for manufacturing a self-assembled nano-scale LED electrode assembly in which a nano-scale LED device can be self-aligned on two different electrodes without being chemically and physically damaged and the number of nano-scale LED devices to be mounted can be remarkably increased, and alignment and electrical connection of the LED devices can be further improved.

Abstract: A test and measurement instrument including a splitter configured to split an input signal into at least two split signals, at least two harmonic mixers configured to mix an associated split signal with an associated harmonic signal to generate an associated mixed signal, at least two digitizers configured to digitize the associated mixed signal, at least two MIMO polyphase filter arrays configured to filter the associated digitized mixed signal of an associated digitizer of the at least two digitizers, at least two pairs of band separation filters configured to receive the associated digitized mixed signals from each of the MIMO polyphase filter arrays and output a low band of the input signal and a high band of the input signal based on a time different between the at least two digitizers and a phase drift of a local oscillator, and a combiner configured to combine the low band of the input signal and the high band of the input signal to form a reconstructed input signal.

Abstract: The present invention provides a transistor and a fabrication method thereof. By a silicon nanowire as a core region being serially wrapped by a germanium channel, a gate insulating film and a gate, the present invention enables to form a potential well for storing holes as a carrier of HHMT in the germanium channel by a valance band energy offset between the silicon core region and the germanium channel, to gain maximum gate controllability to the germanium channel, and to simplify a fabricating process by simultaneously forming the germanium channel and the gate insulating film in one process.

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

Abstract: Some embodiments of the present disclosure describe a multi-layer package with a bi-layered dielectric structure and associated techniques and configurations. In one embodiment, an integrated circuit (IC) package assembly includes a dielectric structure coupled with a metal layer, with the dielectric structure including a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer and a dielectric loss tangent greater than a dielectric loss tangent of the second layer. Other embodiments may be described and/or claimed.

Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor substrate having multiple doped regions forming at least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation, and an electrical transfer element coupled to the semiconductor substrate and operable to transfer an electrical signal from the at least one junction. In one aspect, the textured region is operable to facilitate generation of an electrical signal from the detection of infrared electromagnetic radiation. In another aspect, interacting with electromagnetic radiation further includes increasing the semiconductor substrate's effective absorption wavelength as compared to a semiconductor substrate lacking a textured region.

Abstract: An array substrate and a manufacturing method therefor. The method comprises: patterning a first metal layer by means of a first photomask so as to form a gate electrode (21) and a first conductor (22) which are arranged at an interval; patterning a semiconductor layer (40) and a gate insulating layer (30) by means of a second photomask so as to form a through hole (23) which Is exposed out of the first conductor (22); patterning the semiconductor layer (40) by means of the gate electrode (21) and the first conductor (22) so as to form a first channel region (43) and a second channel region (44) which are arranged at an interval; and patterning a second metal layer by means of a third photomask so as to form a source electrode (51), a drain electrode (52) and a second conductor (53) which are arranged at intervals, wherein the second conductor (53) is in contact with the first conductor (22) via the through hole (23).

Abstract: A TFT array substrate includes parallel data lines parallel extend along a first direction, parallel scan lines crossing the data lines and extending along a second direction perpendicular to the second direction, pixels defined by the data lines and the scan lines, and a common electrode having a main line and growth lines. The main line is parallel to the scan lines. The growth lines extend from the main line. Each pixel includes a pixel electrode, a TFT, partial of the main line, and two growth lines. The TFT is electrically connected to the pixel electrode, a corresponding data line, and a corresponding scan line. The projections of the two growth lines in the pixel overlap with the pixel electrode. Each pixel includes common areas. The common areas overlapping with the two growth lines.

Abstract: The disclosure provides a manufacturing method for TFT array substrate, a TFT array substrate and a display device. The manufacturing method includes following steps: in sequence, forming a gate pattern layer, a gate insulating layer, a patterned poly-silicon layer, a separation layer on s substrate, and adopting a mask to form a source pattern layer and a drain pattern layer on the separation layer by photolithography processes. The source pattern layer and the drain pattern layer are connected to the patterned poly-silicon layer. The mask blocks one side of the channel area, and the same mask is adopted to form a lightly doped area on the other side of the channel area not blocked by the mask. The disclosure may reduce production costs and has great design flexibility.

Abstract: A diode includes: a semiconductor substrate; a cathode metal layer contacting a bottom of the substrate; a semiconductor drift layer on the substrate; a graded aluminum gallium nitride (AlGaN) semiconductor barrier layer on the drift layer and having a larger bandgap than the drift layer, the barrier layer having a top surface and a bottom surface between the drift layer and the top surface, the barrier layer having an increasing aluminum composition from the bottom surface to the top surface; and an anode metal layer directly contacting the top surface of the barrier layer.

Abstract: A compound semiconductor device includes: an electron transit layer; an electron supply layer formed over the electron transit layer; and a GaN cap layer formed over the electron supply layer, wherein the electron supply layer includes a first layer made of i-type AlxGa1-xN (0<x<1) and a second layer made of i-type AlyGa1-yN (x<y?1) and formed over the first layer.

Abstract: A power electronic substrate includes a metallic baseplate having a first and second surface opposing each other. An electrically insulative layer also has first and second surfaces opposing each other, its first surface coupled to the second surface of the metallic baseplate. A plurality of metallic traces each include first and second surfaces opposing each other, their first surfaces coupled to the second surface of the electrically insulative layer. At least one of the metallic traces has a thickness measured along a direction perpendicular to the second surface of the metallic baseplate that is greater than a thickness of another one of the metallic traces also measured along a direction perpendicular to the second surface of the metallic baseplate. In implementations the electrically insulative layer is an epoxy or a ceramic material. In implementations the metallic traces are copper and are plated with a nickel layer at their second surfaces.

Abstract: A sun positioning sensor and method of accurately tracking the sun are disclosed. The sensor includes a position sensing diode and a disk having a body defining an aperture for accepting solar light. An extension tube having a body that defines a duct spaces the position sensing diode from the disk such that the solar light enters the aperture in the disk, travels through the duct in the extension tube and strikes the position sensing diode. The extension tube has a known length that is fixed. Voltage signals indicative of the location and intensity of the sun are generated by the position sensing diode. If it is determined that the intensity values are unreliable, then historical position values are used from a table. If the intensity values are deemed reliable, then actual position values are used from the position sensing diode.

Abstract: An intelligent power module (IPM) has a first, second, third and fourth die paddles, a first, second, third, fourth, fifth and sixth transistors, a tie bar, a low voltage IC, a high voltage IC, a first, second and third boost diodes, a plurality of leads and a molding encapsulation. The first transistor is attached to the first die paddle. The second transistor is attached to the second die paddle. The third transistor is attached to the third die paddle. The fourth, fifth and sixth transistor s are attached to the fourth die paddle. The low and high voltage ICs are attached to the tie bar. The molding encapsulation encloses the first, second, third and fourth die paddles, the first, second, third, fourth, fifth and sixth transistors, the tie bar, the low and high voltage ICs, and the first, second and third boost diodes. The IPM has a reduced top surface area and a reduced number of leads compared to a conventional IPM.

Abstract: Methods, tools and systems for patterning of substrates using charged particle beams without photomasks, without a resist layer, using multiple different processes (different chemistry processes and/or different ones of material deposition, removal and/or modification) in the same vacuum space, wherein said processes are performed independently (without cross-interference) and simultaneously. As a result, the number of process steps can be reduced and some lithography steps can be eliminated, reducing manufacturing cycle time and increasing yield by lowering the probability of defect introduction. Also, because such processes are resist-less, layer-to-layer registration and other column control processes can be performed by imaging previous-layer features local to (or in contact with) features to be written in a next layer as designated by the design layout database.

Abstract: A thin film transistor including a gate electrode, a semiconductor layer, a gate insulating layer, a source electrode, a drain electrode and a graphene pattern. The semiconductor layer overlaps with the gate electrode. The gate insulating layer is disposed between the gate electrode and the semiconductor layer. The source electrode overlaps with the semiconductor layer. The drain electrode overlaps with the semiconductor layer. The drain electrode is spaced apart from the source electrode. The graphene pattern is disposed between the semiconductor layer and at least one of the source electrode and the drain electrode.