Abstract: A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second, opposite, conductivity type below the channel. The back gate is laterally aligned with the channel layer. The semiconductor device is formed by forming a channel mask over the substrate of the semiconductor device which exposes an area for the channel dopants. The channel dopants are implanted into the substrate in the area exposed by the channel mask while the channel mask is in place. The back gate dopants are implanted into the substrate while the channel mask is in place, so that the implanted channel dopants are laterally aligned with the implanted channel dopants.

Abstract: The method for processing signals originating for example from several proximity sensors for the recognition of a movement of an object, comprises first respective samplings of the said signals delivered by the sensors so as to obtain a first set of first date-stamped samples, the generation, from the first set of first date-stamped samples, of new sampling times comprising a start of movement time, an end of movement time, and times regularly spaced between the start of movement time and the end of movement time, a re-sampling of the signal delivered by each sensor between the start of movement time and the end of movement time at the said new sampling times using the first samples, in such a manner as to generate a second set of second date-stamped samples, and a processing of the said second set of date-stamped samples by a movement recognition algorithm.

Abstract: A light-emitting element, a light-emitting element unit and a light-emitting element package are provided, which are each reduced in reflection loss and intra-film light absorption by suppressing multiple light reflection in a transparent electrode layer and hence have higher luminance. The light-emitting element 1 includes a substrate 2, an n-type nitride semiconductor layer 3, a light-emitting layer 4, a p-type nitride semiconductor layer 5, a transparent electrode layer 6 and a reflective electrode layer 7, and the transparent electrode layer 6 has a thickness T satisfying the following expression (1): 3 ? ? 4 ? n + 0.30 × ( ? 4 ? n ) ? T ? 3 ? ? 4 ? n + 0.45 × ( ? 4 ? n ) ( 1 ) wherein ? is the light-emitting wavelength of the light-emitting element 4, and n is the refractive index of the transparent electrode layer 6.

Abstract: A field plate trench FET includes a substrate, a gate buried at least partly within the substrate, and a field plate disposed below the gate, both the gate and the field plate being disposed within a trench in the substrate and being surrounded by an insulator. A p-doped domain is disposed within the substrate below the trench. Also described is a semiconductor component having a substrate and a plurality of field plate trench FETs disposed within the substrate.

Abstract: A semiconductor structure includes a memory unit structure. The memory unit structure includes a transistor, a first electrode, two second electrode, and two resistive random access memory (RRAM) elements. The first electrode and the two second electrodes are disposed in a horizontal plane. The first electrode is disposed between the two second electrodes. The first electrode and the two second electrodes are disposed in parallel. The first electrode is coupled to a source region of the transistor. One of the two RRAM elements is disposed between the first electrode and one of the two second electrodes. The other one of the two RRAM elements is disposed between the first electrode and the other one of the two second electrodes.

Abstract: An interlayer dielectric material includes a planar surface that exhibits planarity due to raster-patterned decomposition products due to use of a confocal light beam. The planar surface encompasses a filled via that is in electrical and physical contact with a bond pad that is also on the planar surface.

Abstract: A semiconductor device according to the present invention includes a semiconductor layer of SiC of a first conductivity type, a plurality of body regions of a second conductivity type formed in the surface portion of the semiconductor layer with each body region forming a unit cell, a source region of the first conductivity type formed in the inner portion of the body region, a gate electrode facing the body region across a gate insulating film, a drain region of the first conductivity type and a collector region of the second conductivity type formed in the rear surface portion of the semiconductor layer such that the drain region and the collector region adjoin each other, and a drift region between the body region and the drain region, wherein the collector region is formed such that the collector region covers a region including at least two unit cells in the x-axis direction along the surface of the semiconductor layer.

Abstract: Embodiments of the invention include a light emitting diode (UVLED), the UVLED including a semiconductor structure with an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. The UVLED is disposed on a mount. A transparent encapsulant is disposed over the UVLED. The transparent encapsulant has an angled sidewall.

Abstract: A light-emitting diode (LED) chip includes a substrate, a light-emitting component, an electrical static discharge (ESD) protection component, and a conductive layer. The light-emitting component is disposed on the substrate and includes a first semiconductor layer, a first quantum well layer, and a second semiconductor layer, in which the first quantum well layer is disposed between the first and second semiconductor layers. The ESD protection component is disposed on the substrate and includes a third semiconductor layer, a second quantum well layer, and a fourth semiconductor layer, in which the second quantum well layer is disposed between the third and the fourth semiconductor layers. The first and the fourth semiconductor layers are electrically connected with each other through the conductive layer, and the second and the third semiconductor layers are electrically isolated from each other before packaging the LED chip.

Abstract: A method is provided for fabricating a semiconductor structure. The method includes providing a substrate having a dielectric layer formed on the substrate, where an opening is formed in the dielectric layer, and bottom of the opening exposes surface of the substrate. The method also includes forming a first metal layer over of the dielectric layer, where a temperature for forming the first metal layer is a first temperature. In addition, the method includes forming a second metal layer filling the opening, where a temperature for forming the second metal layer is a second temperature, and the second temperature is higher than the first temperature. Further, the method includes planarizing the second metal layer and the first metal layer until the top surface of the dielectric layer is exposed.

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Abstract: A power module has a lead frame, a first power chip, a second power chip, a plurality of single in-line leads, a gate drive and protection integrated circuit (IC), a plurality of bonding wires and a molding encapsulation. The first and second power chips are attached to a top surface of the lead frame. The plurality of single in-line leads has a high voltage power lead, a low voltage power lead and a plurality of signal control leads. The low voltage power lead has a lead portion and an extension portion. The gate drive and protection IC is attached to the extension portion of the low voltage power lead. The molding encapsulation encloses the first and second power chips, the extension portion of the low voltage power lead, the gate drive and protection IC, the plurality of bonding wires and at least a majority portion of the lead frame.

Abstract: A method for manufacturing a semiconductor device includes: preparing a first substrate; forming a metal film having a Ti layer as the most outermost surface on one surface of the first substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a first pad portion; preparing a second substrate; forming on one surface of the second substrate a metal film having a Ti layer as the outermost surface; patterning the metal film to form a second pad portion; vacuum annealing the first substrate and the second substrate to remove an oxide film formed on the Ti layer in the first pad portion and the second pad portion; and bonding the first pad portion and the second pad portion together.

Abstract: Use of a single alloy conductor to form simultaneous ohmic contacts (SOC) to n- and p-type 4H-SiC. The single alloy conductor also is an effective diffusion barrier against gold (AU) and oxygen (O2) at high temperatures (e.g., up to 800° C.). The innovation may also provide an effective interconnecting metallization in a multi-level metallization device scheme.

Abstract: A battery system includes a battery that couples to an electrical system. The battery system also includes a battery control module that electrically couples to the battery. The battery control module performs a parallel current integration process on an initial state of charge using an actual capacity and a candidate capacity of the battery. Additionally, the battery control module performs a directional comparison between an estimated state of charge of the battery and results of the parallel current integration process. Further, the battery control module determines validity of the estimated state of charge based at least in part on the directional comparison between the estimated state of charge of the battery and the results of the parallel current integration process.

Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

Abstract: The present application involves a railroad track inspection system comprising a plurality of track scanning sensors, a data store, and a scan data processor. The data store is used for storing track scan data recorded by the track scanning sensors. The scan data processor is used for automatic analysis of the track scan data upon receipt thereof to detect one or more track components within the scan data from a predetermined list of component types according to one or more features identified in said scan data. The system comprises a common support structure to which the track scanning sensors, the data store and scan data processor are attached, the common support structure having a mounting for attachment of the system to a railway vehicle in use.

Abstract: The present subject matter is directed to a method for estimating rotor blade loads, e.g. a blade root resultant moment, of a wind turbine. In one embodiment, the method includes measuring, via one or more sensors, a plurality of operating parameters of the wind turbine. Another step includes estimating out-of-plane and in-plane forces acting on the rotor blade based at least partially on the plurality of operating parameters. Further, the method includes determining an application point for the out-of-plane and in-plane forces along a span of the rotor blade. A further step includes estimating out-of-plane and in-plane moments of the rotor blade based at least partially on the out-of-plane and in-plane forces and the respective application points. Thus, the method includes calculating the load acting on the rotor blade based at least partially on the out-of-plane and in-plane moments.

Abstract: On a first epitaxial layer of a first conductivity type or a second conductivity type provided on a front surface of a silicon carbide substrate, a mark indicating a crystal axis direction of the silicon carbide substrate within a margin of error of one degree is provided. The mark is created on the silicon carbide substrate by forming the first epitaxial layer of the first conductivity type or the second conductivity type on the front surface of the silicon carbide substrate, detecting a stacking fault from the first epitaxial layer, and confirming the crystal axis direction of the silicon carbide substrate from the detected stacking fault.

Abstract: A voltage detection device controls operation of system main relays to change an applied voltage supplied to detection circuits. An error of each of the detection circuits is corrected on the basis of a detection value of each of the detection circuits when the applied voltage is changed. In particular, an offset value is corrected on the basis of a detection value of each of the detection circuits when the system main relays and booster switches are controlled so that a voltage of a high voltage battery supplied to each of the detection circuits becomes zero. A gain error is further corrected on the basis of a detection value of each of the detection circuits when the system main relays and the booster switches are controlled so that the applied voltage supplied to each of the detection circuits becomes equal to the voltage of the high voltage battery.