Patents Examined by Robert K Carpenter
  • Patent number: 11177331
    Abstract: A semiconductor device includes: a semiconductor chip including a substrate having a first surface and a second surface, which are opposite to each other; a through hole penetrating the substrate; a first conductive pad on the first surface of the substrate; a first bump formed over and electrically connected to the first conductive pad; a second conductive pad on the second surface of the substrate; a second bump formed over and electrically connected to the second conductive pad; and a connection electrode buried in the through hole, the connection electrode electrically connecting the first bump and the second bump.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 16, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hae Kwan Seo
  • Patent number: 11158667
    Abstract: An optoelectronic semiconductor component for the emission of multicolored radiation may have a multiplicity of active regions arranged next to one another. The active regions may be configured as microrods or nanorods and configured to generate primary electromagnetic radiation. A first group of the active regions may respectively be followed in an emission direction by a first luminescence conversion element, which is suitable for converting the primary radiation into first secondary radiation. A second group of the active regions is respectively followed in the emission direction by a second luminescence conversion element, which is suitable for converting the primary radiation into second secondary radiation. The primary radiation, the first secondary radiation, and the second secondary radiation having different colors.
    Type: Grant
    Filed: June 14, 2018
    Date of Patent: October 26, 2021
    Assignee: OSRAM OLED GmbH
    Inventor: Tansen Varghese
  • Patent number: 11158991
    Abstract: A cover for an optoelectronic component includes a body of a first material, the body includes a lower side and, starting from the lower side, a recess for the optoelectronic component, the body includes a side surface adjacent to the lower side, the recess is continued as far as the side surface, a plate of a second material is arranged on the side surface, the second material being transparent for a radiation wavelength of the optoelectronic component, and the body and the plate are connected.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: October 26, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Wolfgang Neumann, Jörn Kampmeier
  • Patent number: 11158735
    Abstract: A vertical power semiconductor transistor device includes: a drain region of a first conductivity type; a body region of a second conductivity type; a drift region of the first conductivity type which separates the body region from the drain region; a source region of the first conductivity type separated from the drift region by the body region; a gate trench extending through the source and body regions and into the drift region, the gate trench including a gate electrode; and a field electrode in the gate trench or in a separate trench. The drift region has a generally linearly graded first doping profile which increases from the body region toward a bottom of the trench that includes the field electrode, and a graded second doping profile that increases at a greater rate than the first doping profile from an end of the first doping profile toward the drain region.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 26, 2021
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Siemieniec, David Laforet, Cedric Ouvrard
  • Patent number: 11152468
    Abstract: Provided is a semiconductor device. A semiconductor device includes a substrate, a buffer layer provided on the substrate, a semiconductor layer provided on the buffer layer, a body region provided at a part of a surface layer of the semiconductor layer, a source region provided at a part of a surface layer of the body region, a drain region provided at a part of the surface layer of the semiconductor layer outside the body region, a gate insulating layer provided to extend from the surface layer of the body region to a predetermined depth, a gate electrode provided on the gate insulating layer, a source electrode provided on the source region, a drain electrode provided on the drain region, and an isolation region provided to extend from the surface layer of the semiconductor layer to above the predetermined depth.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: October 19, 2021
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kunihiro Tsubomi, Tetsuo Endoh, Masakazu Muraguchi
  • Patent number: 11152289
    Abstract: A semiconductor device comprises: a lead-frame comprising a die pad having at least one electrically conductive die pad area an insulating layer applied onto the electrically conductive die pad area. An electrically conductive layer is applied onto the insulating layer with one or more semiconductor dice coupled, for instance adhesively, to the electrically conductive layer. The electrically conductive die pad area, the electrically conductive layer and the insulating layer sandwiched therebetween form at least one capacitor integrated in the device. The electrically conductive die pad area comprises a sculptured structure with valleys and peaks therein; the electrically conductive layer comprises electrically conductive filling material extending into the valleys in the sculptured structure of the electrically conductive die pad area.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: October 19, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Fulvio Vittorio Fontana, Giovanni Graziosi, Michele Derai
  • Patent number: 11133263
    Abstract: An integrated circuit package may be formed including at least one die side integrated circuit device having an active surface electrically attached to an electronic interposer, wherein the at least one die side integrated circuit device is at least partially encased in a mold material layer and wherein a back surface of the at least one die side integrated circuit device is in substantially the same plane as an outer surface of the mold material layer. At least one stacked integrated circuit device may be electrically attached to the back surface of the at least one die side integrated circuit through an interconnection structure formed between the at least one die side integrated circuit device and the at least one stacked integrated circuit device.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Veronica Strong, Aleksandar Aleksov, Henning Braunisch, Brandon Rawlings, Johanna Swan, Shawna Liff
  • Patent number: 11127877
    Abstract: The application concerns a method of manufacturing optoelectronic semiconductor components (1) comprising the following steps: A) Growing a semiconductor layer sequence (3) for generating radiation onto a growth substrate (2), B) Structuring the semiconductor layer sequence (3) into emitter strands (11) so that the semiconductor layer sequence (3) is removed in gaps (12) between adjacent emitter strands (11), C) Applying a passivation layer (4), the semiconductor layer sequence (3) at waveguide contacts (51) remote from the growth substrate (2) and the gaps (12) remaining at least partially free, D) Producing at least one metal layer (50), which extends from the waveguide contacts (51) into the gaps (12), E) Replacing the growth substrate (2) with a carrier (6), F) Making vias (53) in the carrier (6) so that the metal layer (50) and underside contacts (52) of the semiconductor layer sequence (3) facing the carrier (6) are electrically contacted, and removing the carrier (6) between at least some of the emitt
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 21, 2021
    Assignee: OSRAM OLED GMBH
    Inventor: Jens Müller
  • Patent number: 11127866
    Abstract: Approaches for the metallization of solar cells and the resulting solar cells are described. In an example, a method of fabricating a solar cell involves forming a barrier layer on a semiconductor region disposed in or above a substrate. The semiconductor region includes monocrystalline or polycrystalline silicon. The method also involves forming a conductive paste layer on the barrier layer. The method also involves forming a conductive layer from the conductive paste layer. The method also involves forming a contact structure for the semiconductor region of the solar cell, the contact structure including at least the conductive layer.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: September 21, 2021
    Assignees: SunPower Corporation, Total Marketing Services
    Inventors: Richard Hamilton Sewell, David Aaron Randolph Barkhouse, Junbo Wu, Michael Cudzinovic, Paul Loscutoff, Joseph Behnke, Michel Arséne Olivier Ngamo Toko
  • Patent number: 11121312
    Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a magnetic tunneling junction (MTJ) on the metal interconnection; forming a top electrode on the MTJ; and forming a trapping layer on the top electrode for trapping hydrogen. Preferably, the trapping layer includes a concentration gradient, in which a concentration of hydrogen decreases from a top surface of the top electrode toward the MTJ.
    Type: Grant
    Filed: September 8, 2019
    Date of Patent: September 14, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Da-Jun Lin, Tai-Cheng Hou, Bin-Siang Tsai, Ting-An Chien
  • Patent number: 11121339
    Abstract: Embodiments of the present application relate to illumination devices using luminescent nanostructures. An illumination device includes a first conductive layer, a second conductive layer, a hole transport layer, an electron transport layer and a material layer that includes a plurality of luminescent nanostructures. The hole transport layer and the electron transport layer are each disposed between the first conductive layer and the second conductive layer. The material layer is disposed between the hole transport layer and the electron transport layer and includes one or more discontinuities in its thickness such that the hole transport layer and the electron transport layer contact each other at the one or more discontinuities. Resonant energy transfer occurs between the luminescent nanostructures and excitons at the discontinuities.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 14, 2021
    Assignee: Nanosys, Inc.
    Inventors: Emma Rose Dohner, Yeewah Annie Chow, Wenzhuo Guo, Christian Justus Ippen, Jason Travis Tillman, Jonathan Andrew Truskier
  • Patent number: 11121221
    Abstract: Unit cells of a current sensing portion are disposed in a sensing effective region of a main non-operating region. In a sensing non-operating region of the main non-operating region excluding the sensing effective region, an n?-type region that surrounds a periphery of the sensing effective region is disposed in a surface region of the front surface of the semiconductor substrate. In the main non-operating region, a p-type base region disposed in a surface region of the front surface of the semiconductor substrate opposes the sensing effective region across the n?-type region. The p-type base region is fixed at a source potential of the main semiconductor element 11. A field insulating film on the front surface of the semiconductor substrate is thicker at a portion that covers the n?-type region that in other portions.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: September 14, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasuyuki Hoshi
  • Patent number: 11121291
    Abstract: A display device is disclosed. In an embodiment a device includes at least one optoelectronic semiconductor component configured to generate primary radiation, a plurality of pixels, wherein each pixel includes at least a first subpixel configured to generate radiation in a first spectral range and a second subpixel configured to generate radiation in a second spectral range different from the first spectral range, wherein the first and second subpixels are each assigned an active region of the semiconductor component; and a radiation conversion element arranged downstream of at least some of the active regions, wherein the radiation conversion element configured to at least partially convert the primary radiation into a secondary radiation and to radiate the secondary radiation at a narrow angle.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 14, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Peter Brick, Hubert Halbritter, Mikko Perälä
  • Patent number: 11107835
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: August 31, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • Patent number: 11099418
    Abstract: A display device including a substrate; a sealing member surrounding a part of a transmission area of the substrate; a plurality of pixels in a display area of the substrate; an encapsulation substrate facing the substrate with the sealing member between the encapsulation substrate and the substrate; a transparent material layer between the substrate and the encapsulation substrate and corresponding to the transmission area; and a light-shielding portion on the encapsulation substrate and corresponding to the sealing member. A width of the light-shielding portion is greater than a width of the sealing member.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 24, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyunmin Hwang, Jaekyung Go, Dongjo Kim, Youngmin Kim, Chanyoung Park, Dongwon Han
  • Patent number: 11101313
    Abstract: [Object] To provide a solid-state imaging device and an electronic apparatus with further improved performance. [Solution] A solid-state imaging device including: a first substrate on which a pixel unit is formed, and a first semiconductor substrate and a first multi-layered wiring layer are stacked; a second substrate on which a circuit having a predetermined function is formed, and a second semiconductor substrate and a second multi-layered wiring layer are stacked; and a third substrate on which a circuit having a predetermined function is formed, and a third semiconductor substrate and a third multi-layered wiring layer are stacked. The first substrate, the second substrate, and the third substrate are stacked in this order. The pixel unit has pixels arranged thereon. The first substrate and the second substrate are bonded together with the first multi-layered wiring layer and the second semiconductor substrate opposed to each other.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: August 24, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hiroshi Horikoshi, Minoru Ishida, Reijiroh Shohji, Tadashi Iijima, Takatoshi Kameshima, Hideto Hashiguchi, Ikue Mitsuhashi, Masaki Haneda
  • Patent number: 11094866
    Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing a semiconductor chip having an active region for radiation emission, applying a seed layer on the semiconductor chip, wherein the seed layer includes a first metal and a second metal being different from the first metal, and wherein the second metal is less noble than the first metal, applying a structured photoresist layer directly to the seed layer and applying a solder layer at least to regions of the seed layer which are not covered by the photoresist layer, wherein a ratio of the first metal to the second metal in the seed layer is between 95:5 to 99:1.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: August 17, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Guido Weiss, Christoph Schwarzmaier, Dominik Scholz, Nicole Heitzer
  • Patent number: 11094628
    Abstract: In some embodiments, integrated inductors may be built using processes for forming interconnects of semiconductor devices without requiring additional process steps. Integrated inductor coils may be formed by, for example, shunting an overlying electrically conductive material, such as, for example, bond pad metals (e.g., aluminum and alloys thereof), to an underlying electrically conductive material, such as, for example, an uppermost layer of wiring formed using Damascene processes (e.g., utilizing copper and alloys thereof), without vias to interconnect the two materials. In some embodiments, integrated inductors formed utilizing such processes may have a symmetric spiral design.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: August 17, 2021
    Assignee: Microchip Technology Incorporated
    Inventor: Yaojian Leng
  • Patent number: 11088224
    Abstract: A display substrate, a manufacturing method and a display device are disclosed. The display substrate includes a base substrate, and a light-shielding layer and a plurality of light-emitting units arranged at a display region of the base substrate. A plurality of imaging pin-holes is formed in the light-shielding layer, an orthogonal projection of each imaging pin-hole onto the base substrate does not overlap an orthogonal projection an active light-emitting region of the corresponding light-emitting unit onto the base substrate, and at least a part of a surface of the light-shielding layer adjacent to the light-emitting units is uneven.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: August 10, 2021
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhen Zhang, Kangguan Pan, Yulong Wei, Kwanggyun Jang, Sanghun Kang, Jun Yan
  • Patent number: 11088349
    Abstract: A display module includes a base substrate including an upper surface where a display area and a non-display area are defined, a lower surface, and a plurality of side surfaces, a circuit element layer including a planarization layer, a pixel defining layer defining an opening portion that overlaps the display area and exposes a portion of the planarization layer, a display element layer including a first electrode disposed on the planarization layer exposed by the opening part, a light emitting layer, and a second electrode, and a sealing layer disposed on the display element layer. A dam hole is defined, which is adjacent to an edge where two side surfaces of the side surfaces are connected in a plan view of the base substrate, overlaps the non-display area, and penetrates at least one of the planarization layer and the pixel defining layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Donghyun Yang, Inkyung Yoo, Sungbae Ju