Abstract: A latch circuit includes a write driving unit configured to output fuse data as boot-up data according to a fuse set select signal in a boot-up operation; and a latch set configured to latch the boot-up data when a latch select signal is activated in the boot-up operation, and output data latched as the latch select signal is activated as a repair column address in a normal operation.

Abstract: A semiconductor memory device includes a memory cell unit including a plurality of memory banks each including a pair of a first memory bank and a second memory bank, a sense amplifier group including a plurality of sense amplifier units each including a first sense amplifier and a second sense amplifier coupled to the first memory bank and the second memory bank, respectively, and a control logic block generating a first column selection signal to transfer data of the first memory bank to the first sense amplifier and a second column selection signal to transfer data of the second memory bank to the second sense amplifier, wherein an active section of the first column selection signal overlaps an active section of the second column selection signal.

Abstract: Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells. Therefore, data of the memory is discriminated by analyzing distribution of the digital code values to monitor a characteristic of a current memory cell array and read the data having reliability.

Abstract: A semiconductor device includes a first vertical memory string connected to a common source line, a second vertical memory string connected to a bit line, a pipe transistor suitable for selectively connecting the first and second vertical memory strings based on a block selection signal, and a plurality of transistors suitable for selectively connecting local lines of the first and second vertical memory strings to corresponding global lines based on the block selection signal.

Abstract: A memory module includes a command/address (CA) register, memory devices, and a module resistor unit mounted on a circuit board. The centrally disposed CA register drive the memory devices one or more internal CA signal(s) to arrangements of memory devices using multiple CA transmission lines, wherein the multiple internal CA transmission lines are commonly terminated in the module resistor unit.

Abstract: A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

Abstract: A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.

Abstract: A memory device may include a plurality of memory banks, a row control signal input unit suitable for receiving a plurality of row control signals, a column control signal input unit suitable for receiving a plurality of column control signals, a row control unit suitable for selecting a memory bank and a row in response to the row control signals, and controlling a row operation for the selected row, and a column control unit suitable for selecting a memory bank and column in response to the column control signals, and controlling a column operation for the selected column.

Abstract: Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.

Abstract: A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.

Abstract: Techniques are presented for reducing the loading on the source lines for NAND type memories that decode memory blocks in multi-block groups, an example 3D NAND memory of the BiCS type. When multiple blocks are commonly decoded, a decoded group may include both selected and unselected blocks. The word lines of a selected block are biased according the operation, while the word lines of the non-selected blocks of the group are set at the level of the source line. This reduces the amount of loading on the source line due to less capacitance between the source line and word lines.

Abstract: MRAM element having a magnetic tunnel junction including a reference layer, a storage layer, a tunnel barrier layer between the reference and storage layers, and a storage antiferromagnetic layer. The storage antiferromagnetic layer has a first function of exchange-coupling a storage magnetization of the storage layer and a second function of heating the magnetic tunnel junction when a heating current in passed in the magnetic tunnel junction. The MRAM element has better data retention and low writing temperature.

Abstract: Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.

Abstract: According to an example embodiment of inventive concepts, an operating method of a non-volatile memory device includes: performing a first hard decision read operation that includes applying a first voltage if a selected word line of the non-volatile memory device; storing a result of the first hard decision read operation at a first latch of a page buffer in the non-volatile memory device; performing a second hard decision read operation that includes applying a second voltage to the selected word line, the second voltage being higher than the first voltage; and generating a first soft decision value using a result of the first hard decision read operation stored at the first latch.

Abstract: Methods of operating a memory device having embedded leak checks may mitigate data loss events due to access line defects, and may facilitate improved power consumption characteristics. Such methods might include applying a program pulse to a selected access line coupled to a memory cell selected for programming, verifying whether the selected memory cell has reached a desired data state, bringing the selected access line to a first voltage, applying a second voltage to an unselected access line, applying a reference current to the selected access line, and determining if a current flow between the selected access line and the unselected access line is greater than the reference current.

Abstract: A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.

Abstract: In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and second components; and buffering, by a second buffer, the first component. The method includes receiving, by a control logic block, the output of the second buffer. The method includes, after a period when the values of both the first and second components are at a first logic state, but before receiving a burst of clock edges in the differential strobe signal, detecting a transition in the first component from the first logic state to a second logic state, and in response to the detected transition, asserting an enable signal. The method further includes receiving, by a gating logic block, the enable signal and the output of the first buffer, and, when the enable signal is asserted, un-gating the output of the first buffer.

Abstract: A semiconductor memory device comprising a memory cell array with a plurality of word lines, first and second dummy word lines, and a dummy word line driver suitable for separately driving the first and second dummy word lines for a wafer burn-in test where the word lines are driven by group.

Abstract: A control circuit provides an at least partially negative threshold voltage distribution to a memory cell, thereby erasing retained data of the memory cell, and provides multiple levels of positive threshold voltage distributions thereto, thereby programming multiple levels of data to the memory cell. The control circuit, when executing a program operation to the memory cell, executes a first program operation that provides the multiple levels of positive threshold voltage distributions to a first memory cell which is a memory cell subject to program, and executes a second program operation that provides a positive threshold voltage distribution, to a second memory cell adjacent to the first memory cell, irrespective of (regardless of) whether data to be programmed to the second memory cell is (already) present in the second memory cell or not.

Abstract: According to one embodiment, a semiconductor memory device includes the following structure. A memory cell array includes memory cells arranged at positions where bit lines and word lines cross are arranged on a semiconductor substrate. A sense amplifier reads data stored in the memory cell. The hookup region includes a transfer transistor arranged between the memory cell array and the sense amplifier. One end of a current path of the transfer transistor is connected to a first interconnect formed between the semiconductor substrate and the bit line. The other end of the current path is connected to the sense amplifier. A guard ring region is arranged between the memory cell array and the hookup region. A contact plug is arranged to overlap the guard ring region.