Abstract: The disclosed subject matter relates to a non-volatile memory bit cell (500 or 600) for solid-state data storage, including, e.g., an elongated magnetic element (102) or “dot”. For appropriate geometry and dimensions of the dot, a two-fold, energetically-degenerate micromagnetic configuration (100 or 200) can be stabilized. Such a stable configuration can consist of two magnetic vortices (1081, 1082) and a flower state region (110). Due to energy minimization, the flower state region can be off-center (relative to a minor axis (106)) and along the major axis (104) of the dot. An electrical current (302) flowing perpendicular to the plane at, or in proximity to, the dot center can, according to current polarity, switch the configuration or state of the dot between the two specular magnetically stable configurations (e.g., a write operation). Reading of the cell state can be accomplished by using the magnetoresistive effect.

Abstract: A nonvolatile semiconductor memory device including: a memory cell array including NAND strings; a plurality of word lines; a plurality of bit lines; a source line; and a control circuit configured to execute a write operation. The control circuit is configured to, when charging an unselected memory string prior to the write operation, execute both first and second charging operations, the first charging operation applying to the bit line connected to the unselected memory string a first voltage and rendering conductive a first select transistor to charge the unselected memory string, and the second charging operation applying to the source line connected to the unselected memory string a second voltage and rendering conductive a second select transistor to charge the unselected memory string, the first and second charging operations being executed at different timings.

Abstract: Techniques for sensing the threshold voltage of a memory cell during reading and verify operations by compensating for changes, including temperature-based changes, in the resistance of a bit line or other control line. A memory cell being sensed is in a block in a memory array and the block is in a group of blocks. A portion of the bit line extends between the group of blocks and a sense component and has a resistance which is based on the length/distance and the temperature. Various parameters can be varied with temperature and the group of blocks to provide the compensation, including bit line voltage, selected word line voltage, source line voltage, sense time and/or sense current or voltage.

Abstract: A magnetoresistance effect element including a recording layer of high thermal stability to perform perpendicular magnetic recording within a film surface, and a magnetic memory using the element. The element includes: a first ferromagnetic layer of an invariable magnetization direction; a second ferromagnetic layer of a variable magnetization direction; a first non-magnetic layer between the first and second ferromagnetic layers; current supply terminals connected to the first and second ferromagnetic layers; a non-magnetic coupling layer on a surface of the second ferromagnetic layer opposite the first non-magnetic layer; a third ferromagnetic layer of a variable magnetization direction on a surface of the non-magnetic coupling layer opposite the second ferromagnetic layer; and a second non-magnetic layer on a surface of the third ferromagnetic layer opposite the non-magnetic coupling layer.

Abstract: A semiconductor memory device and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array with a string. The string comprises a first dummy memory cell and a second dummy memory cell. A circuit is configured to provide a program voltage and one or more operation voltages to the string during a program operation. Control logic is configured to control the circuit to increase a first threshold voltage of the first dummy memory cell and to increase a second threshold voltage of the second dummy memory cell. The first threshold voltage and a second threshold voltage increase by a hot carrier injection mechanism.

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column has an active mode of operation where a read operation may be performed on an activated memory cell within that column group, and a non-active mode of operation where the read operation is not performable. Precharge circuitry is used, for each column group, to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell includes coupling circuitry connected between the associated read bit line and a reference line associated with the column group containing that memory cell.

Abstract: A control circuit of SRAM and an operating method thereof are provided. The control circuit includes a memory array, a word-line driver, a boost circuit and a voltage level detecting circuit. The memory array includes a plurality of memory cells. Each memory cell includes a plurality of transistors. The word-line driver is to activate the word-line of the memory array for cell storage data access. The boost circuit is to provide the higher voltage source for the word-line driver and a first operating voltage for boosting the first operating voltage to a second operating voltage. The voltage level detecting circuit is detecting if the first operation voltage needs to be boosted with boost-operation and a detecting-trigger signal and controls the operating of the boost circuit based on the detecting-trigger signal, the first operating voltage and a predetermined voltage.

Abstract: A semiconductor device may include a nonvolatile storage unit, a select signal generation unit suitable for generating a plurality of select signals using a clock, a plurality of storage units suitable for storing data transmitted from the nonvolatile storage unit in response to the plurality of select signals, respectively, and a clock blocking unit suitable for blocking the clock inputted to the select signal generation unit when the data transmitted from the nonvolatile storage unit is the same as the data stored in the plurality of storage units.

Abstract: A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.

Abstract: Memory circuitry comprising an array of 6T bit cells 6 in which columns of bit cells are coupled together via bit line pairs 8 connected to respective sense amplifier circuitry 10 is provided. The sense amplifier circuitry includes an inverter pair 12, 14 and control circuitry which is configured to control the sense amplifier circuitry to operate in a plurality of modes including an offset compensation mode, an amplification mode and a latching mode.

Abstract: Provided are resistive random access memory (ReRAM) cells, each having three or more resistive states and being capable of storing multiple bits of data, as well as methods of fabricating and operating such ReRAM cells. Such ReRAM cells or, more specifically, their resistive switching layer have wide range of resistive states and are capable of being very conductive (e.g., about 1 kOhm) in one state and very resistive (e.g., about 1 MOhm) in another state. In some embodiments, a resistance ratio between resistive states may be between 10 and 1,000 even up to 10,000. The resistive switching layers also allow establishing stable and distinct intermediate resistive states that may be assigned different data values. These layers may be configured to switching between their resistive states using fewer programming pulses than conventional systems by using specific materials, switching pluses, and resistive state threshold.