Patents Examined by Roberts P Culbert
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Patent number: 10510553Abstract: An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.Type: GrantFiled: May 30, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jack Kuo-Ping Kuo, Sheng-Liang Pan, Chia-Yang Hung, Jyu-Horng Shieh, Shu-Huei Suen, Syun-Ming Jang
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Patent number: 10510516Abstract: A semiconductor manufacturing method and semiconductor manufacturing tool for performing the same are disclosed. The semiconductor manufacturing tool includes a plasma chamber, a mounting platform disposed within the plasma chamber, a focus ring disposed within the plasma chamber, and at least one actuator mechanically coupled to the focus ring and configured to move the focus ring vertically. The actuator is configured to move the focus ring vertically when a plasma is present in the plasma chamber.Type: GrantFiled: November 29, 2016Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi Lin, Yi-Wei Chiu, Hung Jui Chang, Chin-Hsing Lin
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Patent number: 10479911Abstract: The invention provides a chemical-mechanical polishing composition comprising (a) an abrasive comprising colloidal silica and fused silica, (b) a compound of formula (I) or a combination of a compound of formula (II) and a hydrophobic organic compound, (c) an amino acid, (d) hydrogen peroxide, and (e) water, wherein the polishing composition has a pH of about 1 to about 5. The invention also provides a method of chemically-mechanically polishing a substrate, especially a nickel-phosphorous substrate, by contacting the substrate with the inventive chemical-mechanical polishing composition.Type: GrantFiled: June 5, 2018Date of Patent: November 19, 2019Assignee: Cabot Microelectronics CorporationInventor: Selvaraj Palanisamy Chinnathambi
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Patent number: 10483119Abstract: The present disclosure relates to integrated circuit device manufacturing processes. A self-aligned double patterning method is provided. In the method, a lithography process for line cut that determines the locations of line termini is performed after forming a spacer layer alongside the mandrel and prior to stripping the mandrel. The lithographic mask for the line cut is aligned to the mandrel and the spacer layer using a mark made of the mandrel material and the spacer material. Compared to the previous approach where the line cut process is performed after the mandrel removal, in the disclosed approach, the line termini mask is made of the mandrel material and the spacer material, and is more distinguishable compared to a mark made of just the spacer material. Thereby, the methods provide robust photo alignment signal for the line cut photolithography and precise positioning of the line termini mask.Type: GrantFiled: October 16, 2018Date of Patent: November 19, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jui-Yu Pan, Kuo-Chyuan Tzeng, Lee-Chuan Tseng, Ying-Hua Chen
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Patent number: 10478984Abstract: A method for forming a cutting tool includes masking a metal base with one or more masks, the one or more masks including at least one variable permeability mask, and chemically etching the masked metal base to form a blade of the cutting tool.Type: GrantFiled: December 18, 2017Date of Patent: November 19, 2019Assignee: Hutchinson Technology IncorporatedInventors: Paul V. Pesavento, Peter F. Ladwig, Michael W. Davis, John A. Theget, Kurt C. Swanson, Joel B. Michaletz, Philip W. Anderson, Timothy A. McDaniel
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Patent number: 10475662Abstract: A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.Type: GrantFiled: October 12, 2018Date of Patent: November 12, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Wei-Hsin Liu, Ying-Chih Lin, Jui-Min Lee, Gang-Yi Lin, Fu-Che Lee
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Patent number: 10468270Abstract: A planarization process is performed to a wafer. In various embodiments, the planarization process may include a chemical mechanical polishing (CMP) process. A byproduct generated by the planarization process is collected and analyzed. Based on the analysis, one or more process controls are performed for the planarization process. In some embodiments, the process controls include but are not limited to process endpoint detection or halting the planarization process based on detecting an error associated with the planarization process.Type: GrantFiled: January 25, 2018Date of Patent: November 5, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chunhung Chen, Sheng-Chen Wang, Chin Wei Chuang
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Patent number: 10465096Abstract: Provided are Chemical Mechanical Planarization (CMP) formulations that offer high and tunable Cu removal rates and low copper dishing for the broad or advanced node copper or Through Silica Via (TSV). The CMP compositions provide high selectivity of Cu film vs. other barrier layers, such as Ta, TaN, Ti, and TiN, and dielectric films, such as TEOS, low-k, and ultra low-k films. The CMP polishing formulations comprise water; abrasive; single chelator, dual chelators or tris chelators; morpholino family compounds as Cu dishing reducing agents. Additionally, organic quaternary ammonium salt, corrosion inhibitor, oxidizer, pH adjustor and biocide can be used in the formulations.Type: GrantFiled: August 23, 2018Date of Patent: November 5, 2019Assignee: VERSUM MATERIALS US, LLCInventors: Xiaobo Shi, Mark Leonard O'Neill
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Patent number: 10468271Abstract: A dry etching method, including: etching a silicon-containing thin film with a first gas by a first preset thickness; etching the silicon-containing thin film with a second gas by a second preset thickness, to remove etching residues generated after etching the silicon-containing thin film by the first preset thickness; after the etching residues are removed, etching the silicon-containing thin film with the first gas by a third preset thickness, which is less than the first preset thickness; wherein the first gas includes chlorine gas, and the second gas includes fluoride gas.Type: GrantFiled: August 22, 2018Date of Patent: November 5, 2019Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Qingzhao Liu, Jiushi Wang, Lei Zhao
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Patent number: 10453698Abstract: Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.Type: GrantFiled: August 22, 2018Date of Patent: October 22, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-gyo Chung, Yun-seung Kang, Soung-hee Lee, Ji-seung Lee, Hyun-chul Lee
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Patent number: 10453684Abstract: Methods for patterning a film stack are provided. In one embodiment, a method for patterning a film stack disposed on a substrate includes performing a first etching process to etch a film stack disposed on a substrate, wherein the film stack includes a patterned photoresist layer disposed on an upper layer on a lower layer disposed on the substrate, wherein the patterned photoresist layer comprises openings defined between features and the features have a first pitch, wherein the first etching process removes between about 40 percent and about 95 percent of the lower layer exposed by the patterned photoresist layer from the film stack, performing a second etching process on the film stack, and upon completion of the second etching process, transferring the features into the upper or lower layer in the film stack having a second pitch, wherein the second pitch is shorter than the first pitch.Type: GrantFiled: May 9, 2018Date of Patent: October 22, 2019Assignee: Applied Materials, Inc.Inventors: Ying Zhang, Lin Zhou
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Patent number: 10438039Abstract: A glass sensor substrate including metallizable through vias and related process is provided. The glass substrate has a first major surface, a second major surface and an average thickness of greater than 0.3 mm. A plurality of etch paths are created through the glass substrate by directing a laser at the substrate in a predetermined pattern. A plurality of through vias through the glass substrate are etched along the etch paths using a hydroxide based etching material. The hydroxide based etching material highly preferentially etches the substrate along the etch path. Each of the plurality of through vias is long compared to their diameter for example such that a ratio of the thickness of the glass substrate to a maximum diameter of each of the through vias is greater than 8 to 1.Type: GrantFiled: September 14, 2018Date of Patent: October 8, 2019Assignee: Corning IncorporatedInventors: Yuhui Jin, Matthew Evan Wilhelm
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Patent number: 10428241Abstract: Polishing compositions that can selectively and preferentially polish certain dielectric films over other dielectric films are provided herein. These polishing compositions include either cationic or anionic abrasives based on the target dielectric film to be removed and preserved. The polishing compositions utilize a novel electrostatic charge based design, where based on the charge of the abrasives and their electrostatic interaction (forces of attraction or repulsion) with the charge on the dielectric film, various material removal rates and polishing selectivities can be achieved.Type: GrantFiled: October 5, 2017Date of Patent: October 1, 2019Assignee: Fujifilm Electronic Materials U.S.A., Inc.Inventor: Abhudaya Mishra
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Patent number: 10428242Abstract: A slurry composition for chemical mechanical polishing, the slurry composition including ceramic polishing particles; a dispersion agent; a pH control agent and an additive having affinity with silicon nitride.Type: GrantFiled: February 15, 2018Date of Patent: October 1, 2019Assignees: SAMSUNG ELECTRONICS CO., LTD., K.C. TECH Co., Ltd.Inventors: Doo-sik Moon, Sang-hyun Park, Bo-un Yoon, Ho-young Kim, Se-jung Park, Jae-hak Lee, Jin-myung Hwang
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Patent number: 10431472Abstract: A silicon oxide film or a silicon nitride film is selectively etched by using an etching gas composition including a hydrofluorocarbon that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z?2x and y?z are satisfied. Also, a silicon oxide film is etched with high selectivity relative to a silicon nitride film by controlling the ratio among the hydrofluorocarbon, oxygen, argon, etc., included in the hydrofluorocarbon-containing etching gas composition.Type: GrantFiled: October 22, 2018Date of Patent: October 1, 2019Assignee: KANTO DENKA KOGYO CO., LTD.Inventors: Yoshinao Takahashi, Korehito Kato, Tetsuya Fukasawa, Yoshihiko Iketani
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Patent number: 10431458Abstract: Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. In many embodiments, a mask shrink layer is deposited on a patterned mask layer to thereby narrow the openings in the mask layer. The mask shrink layer may be deposited through a vapor deposition process including, but not limited to, atomic layer deposition or chemical vapor deposition. The mask shrink layer can result in narrower, more vertically uniform etched features. In some embodiments, etching is completed in a single etch step. In some other embodiments, the etching may be done in stages, cycled with a deposition step designed to deposit a protective sidewall coating on the partially etched features. Metal-containing films are particularly suitable as mask shrink films and protective sidewall coatings.Type: GrantFiled: November 22, 2016Date of Patent: October 1, 2019Assignee: LAM RESEARCH CORPORATIONInventors: Eric A. Hudson, Mark H. Wilcoxson, Kalman Pelhos, Hyunjong Shim, Merrett Wong
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Patent number: 10424491Abstract: An etching method for etching a silicon-containing layer into a pattern of a mask is provided. The mask is formed by etching, from a block copolymer layer that includes a first polymer and a second polymer, that is layered on the silicon-containing layer of an object to be processed via an intermediate layer, and that is enabled to be self-assembled, a second region including the second polymer and the intermediate layer right under the second region. The etching method includes generating plasma by supplying a process gas including carbon C, sulfur S, and fluorine F to the inside of a processing chamber of a plasma processing apparatus in which the object to be processed is provided; and forming a protective film on the mask and etching the silicon-containing layer according to the generated plasma.Type: GrantFiled: November 15, 2016Date of Patent: September 24, 2019Assignee: Tokyo Electron LimitedInventors: Yuki Takanashi, Noriaki Oikawa
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Patent number: 10418248Abstract: Disclosed is a method of chemically-mechanically polishing a substrate. The method comprises, consists of, or consists essentially of (a) contacting a substrate containing at least one Group III-V material, with a polishing pad and a chemical-mechanical polishing composition comprising water, abrasive particles having a negative surface charge, and an oxidizing agent for oxidizing the Group III-V material in an amount of from about 0.01 wt. % to about 5 wt. %, wherein the polishing composition has a pH of from about 2 to about 5; (b) moving the polishing pad and the chemical-mechanical polishing composition relative to the substrate; and (c) abrading at least a portion of the substrate to polish the substrate. In some embodiments, the Group III-V material is a semiconductor that includes at least one element from Group III of the Periodic Table and at least one element from Group V of the Periodic Table.Type: GrantFiled: February 15, 2017Date of Patent: September 17, 2019Assignee: Cabot Microelectronics CorporationInventors: Benjamin Petro, Glenn Whitener, William Ward
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Patent number: 10414947Abstract: The invention provides a chemical-mechanical polishing composition including wet-process ceria particles having a median particle size of about 25 nm to about 150 nm and a particle size distribution of about 300 nm or more, and an aqueous carrier. The invention also provides a method of polishing a substrate, especially a substrate comprising a silicon layer, with the polishing composition.Type: GrantFiled: February 29, 2016Date of Patent: September 17, 2019Assignee: Cabot Microelectronics CorporationInventors: Brian Reiss, Viet Lam, Renhe Jia
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Patent number: 10414019Abstract: An object of the present invention is to provide a polishing composition enabling polishing of an object to be polished at higher speed. Provided is a polishing composition used for polishing an object to be polished in which the polishing composition contains surface-modified abrasive grains, in which an ionic dispersant is directly modified on the surface of the abrasive grains, and dispersing medium, and aggregation of the abrasive grains is suppressed in the dispersing medium.Type: GrantFiled: September 21, 2016Date of Patent: September 17, 2019Assignee: FUJIMI INCORPORATEDInventors: Takeki Sato, Yukinobu Yoshizaki, Shogo Onishi
