Patents Examined by Roberts P Culbert
  • Patent number: 10619075
    Abstract: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a self-stopping agent, an aqueous carrier, and optionally, a cationic polymer, and provides a method suitable for polishing a substrate.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: April 14, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Juyeon Chang, Tina C. Li, Viet Lam, Ji Cui, Sarah Brosnan, Chul Woo Nam
  • Patent number: 10619076
    Abstract: The invention provides a chemical-mechanical polishing composition comprising an abrasive, a self-stopping agent, an aqueous carrier, and optionally, a cationic polymer, and provides a method suitable for polishing a substrate.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: April 14, 2020
    Assignee: Cabot Microelectronics Corporation
    Inventors: Alexander W. Hains, Juyeon Chang, Tina C. Li, Viet Lam, Ji Cui, Sarah Brosnan, Chul Woo Nam
  • Patent number: 10611962
    Abstract: An etchant composition is presented. The composition includes: 18 wt % to 25 wt % of a first organic acid compound; 15 wt % to 20 wt % of a second organic acid compound; 8.1 wt % to 9.9 wt % of an inorganic acid compound; 1 wt % to 4.9 wt % of a sulfonic acid compound; 10 wt % to 20 wt % of a hydrogen sulfate salt compound; 1 wt % to 5 wt % of a nitrogen-containing dicarbonyl compound; 1 wt % to 5 wt % of an amino acid derivative compound; 0.1 wt % to 2 wt % of an iron-containing oxidizing agent compound; and a balance amount of water.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: April 7, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Hee Park, Ki Tae Kim, Jin Seock Kim, Gyu-Po Kim, Hyun-Cheol Shin, Dae-Woo Lee, Sang-Hyuk Lee
  • Patent number: 10615036
    Abstract: A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: April 7, 2020
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Kuen-Yu Tsai, Miin-Jang Chen, Samuel C. Pan
  • Patent number: 10604678
    Abstract: A process and composition are disclosed for polishing tungsten containing select quaternary phosphonium compounds at low concentrations to at least reduce corrosion rate of tungsten. The process and composition include providing a substrate containing tungsten; providing a stable polishing composition, containing, as initial components: water; an oxidizing agent; select quaternary phosphonium compounds at low concentrations to at least reduce corrosion rate; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten is polished away from the substrate, and corrosion rate of tungsten is reduced.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 31, 2020
    Assignee: Rohrn and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Lin-Chen Ho, Wei-Wen Tsai, Cheng-Ping Lee
  • Patent number: 10600660
    Abstract: Generation of a deposit can be suppressed and high selectivity can be acquired when etching a first region made of silicon nitride selectively against a second region made of silicon oxide. A method includes preparing a processing target object having the first region and the second region within a chamber provided in a chamber main body of a plasma processing apparatus; generating plasma of a first gas including a gas containing hydrogen within the chamber to form a modified region by modifying a part of the first region with active species of the hydrogen; and generating plasma of a second gas including a gas containing fluorine within the chamber to remove the modified region with active species of the fluorine.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: March 24, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Masahiro Tabata, Sho Kumakura
  • Patent number: 10590562
    Abstract: A regenerative electroless etching process produces nanostructured semiconductors in which an oxidant (Ox1) is used as a catalytic agent to facilitate reaction between a semiconductor and a second oxidant (Ox2) that would be unreactive (or slowly reactive compared to Ox1) in the primary reaction. Ox2 is used to regenerate Ox1, which can initiate etching by injecting holes into the semiconductor valence band. The extent of reaction is controlled by the amount of Ox2 added; the reaction rate, by the injection rate of Ox2. This general strategy is demonstrated specifically to produce highly luminescent nanocrystalline porous, amorphous pillared, and hierarchical porous silicon from the reaction of V2O5 in HF(aq) as Ox1 and H2O2(aq) as Ox2 with a silicon-comprising substrate. The process can be performed on silicon-comprising substrates of arbitrary size and shape including powders, reclaimed shards, wafers, pillared silicon, porous silicon, and silicon nanowires.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: March 17, 2020
    Assignee: West Chester University
    Inventors: Kurt W Kolasinski, Jarno Salonen, Ermei Makila
  • Patent number: 10593518
    Abstract: Methods and apparatus for producing high aspect ratio features in a substrate using reactive ion etching (RIE). In some embodiments, a method comprises flowing a gas mixture of C3H2F4 and a companion gas into a process chamber, forming a plasma from the gas mixture using an RF power source connected to an upper electrode above the substrate and at least one RF bias power source connected to a lower electrode under the substrate, performing an anisotropic etch, via the plasma, of at least one layer of oxide or nitride on the substrate using a pattern mask, reducing power of the at least one RF bias power source to produce deposition of a passivation layer on the at least one layer of oxide or nitride on the substrate, and evacuating the process chamber while interrupting the RF power source to stop plasma formation.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 17, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Daisuke Shimizu, Taiki Hatakeyama, Sean S. Kang, Katsumasa Kawasaki, Chunlei Zhang
  • Patent number: 10593783
    Abstract: In a processing method according to one exemplary embodiment, a first nitrified region of a workpiece is etched. The first nitrified region is provided on a first protrusion made of silicon. The workpiece further has a second protrusion, a second nitrified region, and an organic region. The second protrusion is made of silicon. The second nitrified region contains silicon and nitrogen and is provided on the second protrusion. The organic region covers the first and second protrusions and the first and second nitrified regions. In the processing method, the organic region is partially etched to expose the first nitrified region. Then, a silicon oxide film is formed to cover the surface of an intermediate product produced from the workpiece. Then, the silicon oxide film is etched to expose an upper surface of the first nitrified region. Then, the first nitrified region is isotropically etched.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Takino, Kentarou Fujita, Yusuke Yanagisawa
  • Patent number: 10586711
    Abstract: A substrate processing method of processing a substrate using a block copolymer containing a hydrophilic polymer and a hydrophobic polymer, the substrate processing method includes: a block copolymer coating step of applying the block copolymer onto the substrate on which a predetermined projecting and recessed pattern is formed, to form a coating film of the block copolymer; a polymer separation step of phase-separating the block copolymer into the hydrophilic polymer and the hydrophobic polymer; a polymer removal step of selectively removing the hydrophilic polymer from the phase-separated block copolymer; and after the block copolymer coating step and before the polymer removal step, a film thickness reduction step of reducing a film thickness of the coating film of the block copolymer.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: March 10, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Makoto Muramatsu, Tadatoshi Tomita, Hisashi Genjima, Takahiro Kitano
  • Patent number: 10580657
    Abstract: Systems and methods discussed herein are directed towards processing of substrates, including forming a plurality of features in a target layer on a substrate. The formation of the plurality of features includes a main etch operation that forms the plurality of features to a first depth in the target layer. The main etch operation is followed by a phase shift sync pulsing (PSSP) operation, and these two operations are repeated iteratively to form the features to a predetermined depth. The PSSP operation includes one or more cycles of RF source power and RF bias power, this cycle deposits a protective coating in and on the features and then etches a portion of the protective coating to expose portions of the feature.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 3, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chang Wook Doh, Zhibin Wang, Byungkook Kong, Sang Wook Kim, Sang-Jun Choi
  • Patent number: 10573527
    Abstract: Systems and methods of etching a semiconductor substrate may include flowing an oxygen-containing precursor into a substrate processing region of a semiconductor processing chamber. The substrate processing region may house the semiconductor substrate, and the semiconductor substrate may include an exposed metal-containing material. The methods may include flowing ammonia into the substrate processing region at a temperature above about 200° C. The methods may further include removing an amount of the metal-containing material.
    Type: Grant
    Filed: April 5, 2019
    Date of Patent: February 25, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Geetika Bajaj, Robert Jan Visser, Nitin Ingle, Zihui Li, Prerna Sonthalia Goradia
  • Patent number: 10573529
    Abstract: A method for etching a dielectric layer covering at least one top and at least one flank of a semi-conductive material-based structure is provided, including a plurality of sequences, each including successive steps of: a first etching of the layer by plasma using a chemistry including at least a first fluorine-based compound and a second compound chosen from SiwCl(2w+2) and SiwF(2w+2), w, x, y, and z being whole numbers, and oxygen, the first etching: interrupting before complete consumption of the dielectric layer thickness on the flank and after complete consumption of the thickness on the top, and forming a first protective layer on the top and a second protective layer on the flank; and a second etching fully removing the second layer while conserving a portion of the first layer thickness, each sequence being repeated until complete removal of the dielectric layer on the flank.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 25, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Sebastien Barnola
  • Patent number: 10566208
    Abstract: A plasma etching method for etching a multilayer laminate in which a silicon oxide film and a silicon nitride film are stacked includes an etching step of plasma etching the silicon oxide film and the silicon nitride film using a gas of a non-bromine-containing fluorocarbon together with a gas of a bromine-containing fluorocarbon compound represented by a compositional formula C3H2BrF3.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: February 18, 2020
    Assignee: ZEON CORPORATION
    Inventors: Takaaki Sakurai, Hirotoshi Inui
  • Patent number: 10566204
    Abstract: In some embodiments, a method of forming an integrated circuit includes providing a semiconductor substrate having an electronic circuit formed on a front side, and having a first material layer located over a second side of the substrate and a second material layer located between the first material layer and the second side. At least a portion of the first material layer is removed using a first chemical etching process, thereby exposing the second material layer. At least a portion of the second material layer is removed using a second chemical etching process. A portion of the substrate is then mechanically removed from the second side.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: February 18, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jian Jun Kong, She Yu Tang, Tian Yi Zhang, Qin Xu Yu, Sheng Pin Yang
  • Patent number: 10553431
    Abstract: The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: February 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kuan-Wei Huang, Chia-Ying Lee, Ming-Chung Liang
  • Patent number: 10553446
    Abstract: A method includes anisotropically etching an etching target layer of a target object through an opening of the target object by generating plasma of a first gas within a processing vessel in which the target object is accommodated; and then forming a film on an inner surface of the opening by repeating a sequence comprising: a first process of supplying a second gas into the processing vessel; a second process of purging a space within the processing vessel; a third process of generating plasma of a third gas containing an oxygen atom within the processing vessel; and a fourth process of purging the space within the processing vessel. The first gas contains a carbon atom and a fluorine atom. The second gas contains an aminosilane-based gas. The etching target layer is a hydrophilic insulating layer containing silicon. Plasma of the first gas is not generated in the first process.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: February 4, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihide Kihara, Toru Hisamatsu, Masahiro Tabata
  • Patent number: 10546723
    Abstract: A plasma processing method for a workpiece in a plasma processing apparatus includes (i) performing a first plasma processing on a workpiece, and (ii) performing a second plasma processing on the workpiece. Power of second radio frequency waves set in the second plasma processing is greater than the power of the second radio frequency waves set in the first plasma processing. In the second plasma processing, a magnetic field distribution having a horizontal component on an edge side of the workpiece greater than a horizontal component on a center of the workpiece is formed by an electromagnet.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: January 28, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akihiro Yokota, Takanori Banse, Joji Takayoshi, Shinya Morikita, Naohiko Okunishi
  • Patent number: 10515824
    Abstract: A method of anisotropic etching comprises forming a metal layer above a substrate. A mask layer is formed on the metal layer with openings defined in the mask layer to expose portions of the metal layer. The exposed portions of the metal layer are introduced to an active etchant solution that includes nanoparticles as an insoluble banking agent. In further embodiments, the exposed portions of the metal layer are introduced to a magnetic and/or an electrical field.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Leonel Arana, Nicholas S. Haehn, Hsin-Wei Wang, Oscar Ojeda, Arnab Roy
  • Patent number: 10515782
    Abstract: A system and method for rapid atomic layer etching (ALET) including a pulsed plasma source, with a spiral coil electrode, a cooled Faraday shield, a counter electrode disposed at the top of the tube, a gas inlet and a reaction chamber including a substrate support and a boundary electrode. The method includes positioning an etchable substrate in a plasma etching chamber, forming a product layer on the surface of the substrate, removing a portion of the product layer by pulsing a plasma source, then repeating the steps of forming a product layer and removing a portion of the product layer to form an etched substrate.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: December 24, 2019
    Assignee: UNIVERSITY OF HOUSTON SYSTEM
    Inventors: Vincent M. Donnelly, Demetre J. Economou