Abstract: Multiple sequential processes are conducted in a reaction chamber to form ultra high quality silicon-containing compound layers, including silicon nitride layers. In a preferred embodiment, a silicon layer is deposited on a substrate using trisilane as the silicon precursor. A silicon nitride layer is then formed by nitriding the silicon layer. By repeating these steps, a silicon nitride layer of a desired thickness is formed.

Abstract: Method for producing a field effect transistor having a source region (9), a drain region and a channel layer (11) interconnecting the source and drain regions, and including the step of providing a sacrificial layer (4) on part of a semiconductor material (1) whose edge is used to define the edge of an implant, such as the source region (9), in the semiconductor material (1), where the edge (4c) of the sacrificial layer (4) is subsequently used to define the edge of a gate (16).

Abstract: A substrate processing apparatus, according to which inspection of various devices in the substrate processing apparatus can be carried out with improved reliability, while reducing the burden on a user. A processing chamber processes semiconductor wafers therein. A transfer chamber transfers the semiconductor wafers. A FOUP (front opening unified pod) houses a plurality of dummy wafers for inspection of the processing chamber or the transfer chamber. A CPU causes an HDD (hard disk drive) to store a housing state relating to the arrangement of the dummy wafers in the FOUP before replacement of dummy wafers in the FOUP and that after the replacement as dummy wafer setup information.

Abstract: A double-diffused metal-oxide-semiconductor (“DMOS”) field-effect transistor with an improved gate structure. The gate structure includes a first portion of a first conductivity type for creating electron flow from the source to the drain when a charge is applied to the gate. The gate structure includes a second portion of a second conductivity type having a polarity that is opposite a polarity of the first conductivity type, for decreasing a capacitance charge under the gate. A second structure for decreasing a capacitance under the gate includes an implant region in the semiconductor substrate between a channel region, where the implant region is doped to have a conductivity opposite the channel region.

Abstract: A method of manufacturing a semiconductor device comprises forming a trench in a semiconductor substrate, forming a first insulating film having a first recessed portion in the trench, forming a coating film so as to fill the first recessed portion therewith, transforming the coating film into a second insulating film, planarizing the second insulating film to expose the first insulating film and the second insulating film, removing at least the second insulating film from the first recessed portion to moderate an aspect ratio for the first recessed portion formed in the trench, thereby forming a second recessed portion therein, and forming a third insulating film on a surface of the semiconductor substrate so as to fill the second recessed portion therewith.

Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.

Abstract: Disclosed are techniques and apparatus are provided for determining overlay error or pattern placement error (PPE) across the field of a scanner which is used to pattern a sample, such as a semiconductor wafer or device. This determination is performed in-line on the product wafer or device. That is, the targets on which overlay or PPE measurements are performed are provided on the product wafer or device itself. The targets are either distributed across the field by placing the targets within the active area or by distributing the targets along the streets (the strips or scribe areas) which are between the dies of a field. The resulting overlay or PPE that is obtained from targets distributed across the field may then be used in a number of ways to improve the fabrication process for producing the sample.

Abstract: A gate wire including a gate line and a gate electrode is formed on a substrate and a gate insulating layer is formed on the substrate. A semiconductor pattern and an etching assistant pattern are formed on the gate insulating layer and a source/drain conductor pattern and an etching assistant layer are formed on the semiconductor pattern and the etching assistant pattern. A data wire including a data line and source and drain electrodes separated from each other is formed by removing the etching assistant layer and partly removing the source/drain conductor pattern. A pixel electrode connected to the drain electrodes is formed.

Abstract: A solar module 20 comprises first and second sheets 21 and 22, a plurality of rows (a plurality of groups) of spherical solar cells 11 incorporated in between these sheets 21 and 22 in a state in which the conduction direction is perpendicular to the surface of the sheets, a mechanism for the parallel connection of each group of spherical solar cells 11, a mechanism for the serial connection of each group of spherical solar cells 11 with the spherical solar cells 11 in adjacent groups, a positive electrode terminal 23, and a negative electrode terminal 24. A positive electrode is formed on the bottom and a negative electrode on top in the odd-numbered rows of spherical solar cells 11 from the left end, while a positive electrode is formed on top and a negative electrode on the bottom in the even-numbered rows of spherical solar cells 11.

Abstract: In one aspect of the invention, a method of attaching a semiconductor die to a microarray leadframe is described. The method comprises stamping an adhesive onto discrete areas of the microarray leadframe using a multi-pronged stamp tool. The adhesive is applied to the leadframe as a series of dots, each dot corresponding to an associated prong of the stamping tool. In some embodiments the adhesive used to attach the semiconductor die to a leadframe is a black epoxy based adhesive material. In an apparatus aspect of the invention, lead traces in a microarray leadframe are arranged to have tails that extend beyond their associated contact posts on the side of the contact post that is opposite a wire bonding region such that such lead traces extends on two opposing sides of their associated contact posts. The tails do not attach to other structures within the lead frame (such as a die attach structure).

Abstract: A process for bonding two distinct substrates that integrate microsystems, including the steps of forming micro-integrated devices in at least one of two substrates using micro-electronic processing techniques and bonding the substrates. Bonding is performed by forming on a first substrate bonding regions of deformable material and pressing the substrates one against another so as to deform the bonding regions and to cause them to react chemically with the second substrate. The bonding regions are preferably formed by a thick layer of a material chosen from among aluminum, copper and nickel, covered by a thin layer of a material chosen from between palladium and platinum. Spacing regions ensure exact spacing between the two wafers.

Abstract: Nanotube device structures and methods of fabrication. A method of making a nanotube switching element includes forming a first structure having at a first output electrode; forming second structure having a second output electrode; forming a conductive article having at least one nanotube, the article having first and second ends; positioning the conductive article between said first and second structures such that the first structure clamps the first and second ends of the article to the second structure, and such that the first and second output electrodes are opposite each other with the article positioned therebetween; providing at least one signal electrode in electrical communication with the conductive article; and providing at least one control electrode in spaced relation to the conductive article such that the control electrode may control the conductive article to form a conductive pathway between the signal electrode and the first output electrode.

Abstract: In a semiconductor device having a semiconductor element having a plurality of SOI-Si layers, the height of element isolation regions from the surface of the semiconductor substrate are substantially equal to each other. Alternatively, the element isolation regions are formed at the equal height on the semiconductor substrate and then a plurality of SOI-Si layers appropriately different in thickness are formed. In this manner, it is possible to obtain element isolation regions having substantially the same height from the semiconductor substrate and desired element regions having SOI-Si layers different in height. The thickness of a single crystalline silicon film (SOI-Si layer) may be appropriately changed by another method which includes depositing an amorphous silicon film and applying a heat processing to form an epi layer, and removing an unnecessary portion.

Abstract: To laminate field effect transistors having different conductivity types, while suppressing deterioration of the crystallinity of semiconductor layers where the field effect transistors are formed. A single crystal semiconductor layer, a dielectric layer and a single crystal semiconductor layer are successively laminated on a dielectric layer, a gate electrode is formed on side walls on both sides of the single crystal semiconductor layers through gate dielectric films and formed on side surfaces on both side of the single crystal semiconductor layers, source/drain layers disposed respectively on both sides of the gate electrode are formed in the single crystal semiconductor layer 13a, and source/drain layers disposed respectively on both sides of the gate electrode are formed in the single crystal semiconductor layer, whereby a P-channel field effect transistor MP1 and an N-channel field effect transistor MN1 are laminated.

Abstract: A sensor array includes a substrate including a front side and a back side, a plurality of transducers fabricated on the front side of the substrate, a plurality of input/output connections positioned on the back side of the substrate, the input/output connections electrically coupled to the transducers, at least one electronic device, and an interposer positioned between the substrate and the electronic device, the interposer including a multilayer interconnect system configured to electrically connect the input/output connections to the electronic device.

Abstract: Drain extended MOS transistors (52) and fabrication methods (100) therefor are presented, in which a voltage drop region (80) is provided in a well (82) of a second conductivity type between a channel (78) of a first conductivity type and a drain (74) to inhibit channel hot carrier or direct tunneling degradation of the transistor gate dielectric (64) for high voltage operation. The voltage drop region (80) has more dopants of the first conductivity type and/or fewer dopants of the second conductivity type than does the well (82) so as to shift the high fields away from the transistor gate dielectric (64).

Abstract: A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed.

Abstract: A method of forming a solder bump may involve forming a first photoresist pattern on a wafer having a pad. The first photoresist pattern may have an opening that exposes a portion of the pad. A first under bump metallurgy (UBM) layer may be formed on the pad, and a second UBM layer may be formed on the first photoresist pattern. A second photoresist pattern may be formed that exposes the first UBM layer. A solder bump may be formed in the opening. The second photoresist pattern and the first photoresist pattern may be removed using a stripper, thereby removing the second UBM layer by a lift-off method.

Abstract: An antifuse element (102, 152, 252, 302, 352, 402, 602, 652, 702) and method of fabricating the antifuse element, including a substrate material (101) having an active area (106) formed in an upper surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a gate oxide layer (110) disposed between the gate electrode (104) and the active area (106). The gate oxide layer (110) including the fabrication of one of a gate oxide dip (128) or a gate oxide undercut (614). During operation a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the gate oxide layer (110) and a rupture of the gate oxide layer (110) in a rupture region (130). The rupture region (130) defined by the oxide structure and the gate oxide dip (128) or the gate oxide undercut (614).

Abstract: A method for fabricating a thin film pattern and a method for fabricating a flat panel display device using the same to form an organic material pattern by not using a photo process are disclosed. The method for fabricating the thin film pattern includes forming a first conductive thin film pattern on a substrate; forming a master mold provided with a second thin film pattern; coating an organic material on the master mold provided with the second thin film pattern; joining the substrate and the master mold to contact the first thin film pattern and a surface of the substrate with the organic material; hardening the organic material; separating the substrate and the master mold from each other to provide an organic thin film pattern having step coverage formed by the second thin film pattern on a substrate provided with the first thin film pattern.