Abstract: According to some embodiments of the invention, a method of forming a transistor includes forming a device isolation layer in a semiconductor substrate. The device isolation layer is formed to define at least one active region. A channel region is formed in a predetermined portion of the active region of the semiconductor substrate. Two channel portion holes are formed to extend downward from a main surface of the semiconductor substrate to be in contact with the channel region. Gate patterns fill the channel portion holes and cross the active region. The resulting transistor is capable of ensuring a constant threshold voltage without being affected by an alignment state of the channel portion hole and the gate pattern.

Abstract: Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an opening into a silicate glass-comprising material received over a monocrystalline material. The etching is conducted to the monocrystalline material effective to expose the monocrystalline material at a base of the opening. A silicon-comprising layer is epitaxially grown within the opening from the monocrystalline material exposed at the base of the opening. The silicate glass-comprising material is etched from the substrate effective to leave a free-standing projection of the epitaxially grown silicon-comprising layer projecting from the monocrystalline material which was at the base of the opening. Other implementations and aspects are contemplated.

Abstract: A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

Abstract: The present invention provides, in one embodiment, a process for forming a dual work function metal gate semiconductor device (100). The process includes providing a semiconductor substrate (105) having a gate dielectric layer (110) thereon and a metal layer (205) on the gate dielectric layer. A work function of the metal layer is matched to a conduction band or a valence band of the semiconductor substrate. The process also includes forming a conductive barrier layer (210) on a portion (215) of the metal layer and a material layer (305) on the metal layer. The metal layer and the material layer are annealed to form a metal alloy layer (405) to thereby match a work function of the metal alloy layer to another of the conduction band or the valence band of the substrate. Other embodiments of the invention include a dual work function metal gate semiconductor device (900) and an integrated circuit (1000).

Abstract: Disclosed is an active matrix liquid crystal display device designed mainly for alternating electric current drive, in which orientation processing (monostabilization) is performed by a direct current power supply or a direct current voltage applied to a ferroelectric liquid crystal. The liquid crystal is made to respond, and is made monostable while a voltage level is maintained by a storage capacitor. In addition, the liquid crystal may also be made monostable while maintaining a gate clock pulse at a constant level. After forming a transparent conductive film on an element substrate, elements such as TFTs are formed. An electric field is applied by a direct current voltage source between an electrode formed on an opposing substrate and the transparent conductive film. An electric field is applied by a direct current voltage source between the electrode formed on the opposing substrate and the transparent conductive film formed on the back side of the element substrate.

Abstract: A system and method is disclosed that prevents the formation of a vertical bird's beak structure in the manufacture of a semiconductor device. A polysilicon filled trench is formed in a substrate of the semiconductor device. One or more composite layers are then applied over the trench and the substrate. A mask and etch process is then applied to etch the composite layers adjacent to the polysilicon filled trench. A field oxide process is applied to form field oxide portions in the substrate adjacent to the trench. Because no field oxide is placed over the trench there is no formation of a vertical bird's beak structure. A gate oxide layer is applied and a protection cap is formed over the polysilicon filled trench to protect the trench from unwanted effects of subsequent processing steps.

Abstract: An embodiment of the invention provides a semiconductor fabrication method. The method comprises forming a strained channel region in semiconductor devices. Embodiments include forming a stressor layer over an amorphous portion of the semiconductor device at an intermediate stage of fabrication. The device is masked and strain in a portion of the stressor layer is relaxed. Recrystallizing the amorphous portion of the intermediate device transfers strain from the stressor to the substrate. At least a portion of the strain remains in the substrate through subsequent device fabrication, thereby improving performance of the completed device. In other embodiments, a tensile stressor layer is formed over a first portion of the device, and a compressive stressor layer is formed over a second portion. A tensile stressor layer forms a compressive channel in a PMOS device, and a compressive stressor forms a tensile channel in an NMOS device.

Abstract: A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a flip-chip package that uses an underfill mixture.

Abstract: A method of forming a trench type isolation film of a semiconductor device, including the steps of sequentially forming a pad oxide film and a nitride film for a hard mask on a semiconductor substrate in which a cell region and a peri region are defined; patterning the nitride film using an etch process employing a cell array mask; coating a photoresist on the entire structure including the patterned nitride film; patterning the photoresist using a peri ISO mask; sequentially etching the nitride film, the pad oxide film, and the semiconductor substrate using the patterned photoresist as an etch mask, thereby forming first trenches; stripping the photoresist; etching the semiconductor substrate of the cell region and the peri region using the patterned nitride film as an etch mask, thereby forming second trenches in the cell region and third trenches, which are consecutive to the first trenches, in the peri region; and, forming an isolation film within the second and third trenches.

Abstract: A substrate processing apparatus, according to which inspection of various devices in the substrate processing apparatus can be carried out with improved reliability, while reducing the burden on a user. A processing chamber processes semiconductor wafers therein. A transfer chamber transfers the semiconductor wafers. A FOUP (front opening unified pod) houses a plurality of dummy wafers for inspection of the processing chamber or the transfer chamber. A CPU causes an HDD (hard disk drive) to store a housing state relating to the arrangement of the dummy wafers in the FOUP before replacement of dummy wafers in the FOUP and that after the replacement as dummy wafer setup information.

Abstract: The invention includes a semiconductor structure having U-shaped transistors formed by etching a semiconductor substrate. In an embodiment, the source/drain regions of the transistors are provided at the tops of pairs of pillars defined by crossing trenches in the substrate. One pillar is connected to the other pillar in the pair by a ridge that extends above the surrounding trenches. The ridge and lower portions of the pillars define U-shaped channels on opposite sides of the U-shaped structure, facing a gate structure in the trenches on those opposite sides, forming a two sided surround transistor. Optionally, the space between the pillars of a pair is also filled with gate electrode material to define a three-sided surround gate transistor. One of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The invention also includes methods of forming semiconductor structures.

Abstract: In one illustrative embodiment, the method comprises providing an SOI substrate comprised of an active layer, a buried insulation layer and a bulk substrate, the active layer being doped with a first type of dopant material, the bulk substrate having an inner well formed therein adjacent a surface of the bulk substrate and under the active layer, the inner well being doped with the first type of dopant material, forming a transistor above the SOI substrate in an area above the inner well and applying a voltage to the inner well to vary a threshold voltage of the transistor. In some embodiments, the method further comprises forming an NMOS transistor, wherein the active layer and the inner well are doped with a P-type dopant material. In other embodiments, the method further comprises forming a PMOS transistor, wherein the active layer and the inner well are doped with an N-type dopant material.

Abstract: A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer.

Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.

Abstract: A method and apparatus for electroprocessing a substrate is provided. In one embodiment, a method for electroprocessing a substrate includes the steps of biasing a first electrode to establish a first electroprocessing zone between the electrode and the substrate, and biasing a second electrode disposed radially inward of the first electrode with a bias that is different than the bias applied to the first electrode. In one embodiment, the first electrode is coated with an inert material and in this way the same polish rate is obtained with a lower potential level applied to the first electrode.

Abstract: Power MOSFETs and fabrication processes for power MOSFETs use a continuous conductive gate structure within trenches to avoid problems arising from device topology caused when a gate bus extends above a substrate surface. The gate bus trench and/or gate structures in the device trenches can contain a metal/silicide to reduce resistance, where polysilicon layers surround the metal/silicide to prevent metal atoms from penetrating the gate oxide in the device trenches. CMP process can remove excess polysilicon and metal and planarize the conductive gate structure and/or overlying insulating layers. The processes are compatible with processes forming self-aligned or conventional contacts in the active device region.

Abstract: Methods and apparatus for assessing a constituent in a semiconductor substrate. Several embodiments of the invention are directed toward non-contact methods and systems for identifying an atom specie of a dopant implanted into the semiconductor substrate using techniques that do not mechanically contact the substrate with electrical leads or other types of mechanical measuring instruments. For example, one embodiment of a non-contact method of assessing a constituent in a semiconductor substrate in accordance with the invention comprises obtaining an actual reflectance spectrum of infrared radiation reflected from the semiconductor substrate, and ascertaining a plasma frequency value (?p) and a collision frequency value (?) for the semiconductor substrate based on the actual reflectance spectrum. This method can further include identifying a dopant type based on a relationship between dopant types and (a) plasma frequency values and (b) collision frequency values.

Abstract: Semiconductor devices and methods for fabricating the same are disclosed in which an amorphous layer is formed in an interface between a device isolation layer and a source or drain region to stably thin a silicide layer formed in the interface. A leakage current of the silicide layer formed in the interface between the device isolation layer and the source/drain region is reduced.

Abstract: A semiconductor device is formed by providing a substrate. A trench is formed in the substrate. Beveled surfaces are formed at upper portions of sidewalls of the trench opposite a bottom surface of the trench, respectively. An oxide layer is formed in the trench such that the oxide layer is thicker on the beveled surfaces of the trench than on other surfaces of the trench.

Abstract: A method of forming and resulting isolation region, which allows for densification of an oxide layer in the isolation region. One exemplary embodiment of the method includes the steps of forming a first trench, forming an oxide layer on the bottom and sidewalls of the trench, forming nitride spacers on the lined trench, and thereafter etching the silicon beneath the first trench to form a second trench area. An oxide layer is then deposited to fill the second trench. Densificiation of the isolation region is possible because the silicon is covered with nitride, and therefore will not be oxidized. Light etches are then performed to etch the oxide and nitride spacer area in the first trench region. A conventional oxide fill process can then be implemented to complete the isolation region.