Patents Examined by Rong Tang
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Patent number: 11899064Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.Type: GrantFiled: December 13, 2022Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sandeep Kumar Goel, Yun-Han Lee, Saman M. I. Adham, Marat Gershoig
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Patent number: 11886313Abstract: Systems, apparatus and methods are provided for temperature assisted non-volatile storage device management in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a temperature sensor, a non-volatile storage device and a processor. The processor may be configured to obtain a read-out from the temperature sensor, generate a predicted real-time on-die temperature for the non-volatile storage device based on the read-out, generate an estimated threshold voltage for reading data stored in the non-volatile storage device based on the predicted real-time on-die temperature and conduct a local sweep of a reference voltage using the estimated threshold voltage as a starting point to obtain a final read reference voltage with a minimum read bit error rate.Type: GrantFiled: September 21, 2020Date of Patent: January 30, 2024Assignee: Innogrit Technologies Co., Ltd.Inventors: Gang Zhao, Lin Chen, Wei Jiang, Jie Chen, Tao Wei
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Method for detecting perturbations in a logic circuit and logic circuit for implementing this method
Patent number: 11879938Abstract: A method for detecting perturbations in a logic circuit including a plurality of datapaths coordinated by a clock signal and at least one test circuit having a programmable length datapath for varying a test propagation delay. The test circuit further including inputs, an output and an error generator for providing an error in case that the output is different than an expected output for the inputs. The test circuit having a calibration mode including determining a critical propagation delay by varying the programmable length datapath until the error generator outputs an error, adjusting the programmable length datapath to include therein a tolerance delay, and switching into a detection mode configured to detect a perturbation in the logic circuit along the programmable length datapath in case the error generator outputs an error.Type: GrantFiled: December 21, 2020Date of Patent: January 23, 2024Assignee: Nagravision SàrlInventors: Jean-Marie Martin, Roan Hautier -
Patent number: 11870461Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting (EC) layout constitutes a first layout in the form of a Latin Square.Type: GrantFiled: August 3, 2022Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Wei Wu, Zhenlei Shen, Zhengang Chen
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Patent number: 11842785Abstract: A temperature-accelerated solid-state storage testing method includes writing data to a storage system and subjecting the storage system to a first temperature range for a first time period that is equivalent to operation at a lower/second temperature for a greater/second time period. Subsequently, the data from the storage system is read within a third time period at a third temperature range to generate first test data. The storage system is then subjected to the first temperature range for a fourth time period that was reduced relative to the first time period based on the reading of the data to generate the first test data causing the operation of storage system to be equivalent to operating at the second temperature range for a fifth time period. Subsequently the data from the storage system is read within the third time period at the third temperature range to generate second test data.Type: GrantFiled: April 8, 2022Date of Patent: December 12, 2023Assignee: Dell Products L.P.Inventors: Samuel Hudson, Michael Rijo, Robert Proulx
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Patent number: 11836385Abstract: An embodiment may involve a network interface configured to capture data packets into a binary format and a non-volatile memory configured to temporarily store the data packets received by way of the network interface. The embodiment may also involve a first array of processing elements each configured to independently and asynchronously: (i) read a chunk of data packets from the non-volatile memory, (ii) identify flows of data packets within the chunk, and (iii) generate flow representations for the flows. The embodiment may also involve a second array of processing elements configured to: (i) receive the flow representations from the first array of processing elements, (ii) identify and aggregate common flows across the flow representations into an aggregated flow representation, (iii) based on a filter specification, remove one or more of the flows from the aggregated flow representation, and (iv) write information from the aggregated flow representation to the database.Type: GrantFiled: June 8, 2022Date of Patent: December 5, 2023Assignee: fmad engineering kabushiki gaishaInventor: Aaron Foo
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Patent number: 11824557Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.Type: GrantFiled: November 7, 2022Date of Patent: November 21, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-ho Myung, Kyung-joong Kim, Hong-sil Jeong
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Patent number: 11816339Abstract: Methods, systems, and devices for selectable error control for memory device are described. An apparatus may include a memory array and a circuit configurable to perform a first error control operation and a second error control operation on data stored by the memory array. The circuit may include a first plurality of gates enabled during the first error control operation and configured to generate a first set of bits associated with a first matrix of the first error control operation. The circuit may also include a second plurality of gates enabled during the second error control operation and configured to generate a second set of bits associated with the second matrix of the second error control operation. The circuit may further include a third plurality of gates configured to generate a third set of bits that are common to both the first matrix and the second matrix.Type: GrantFiled: August 2, 2021Date of Patent: November 14, 2023Assignee: Micron Technology, Inc.Inventor: Scott E. Schaefer
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Patent number: 11817878Abstract: A multi-channel decoder circuit associated with a multi-channel decoder system is disclosed. The multi-channel decoder circuit comprises a distributed decoder circuit comprising a set of unit decoder circuits, each unit decoder circuit configured to receive one or more codewords of a plurality of codewords associated with a plurality of input channels, and decode the one or more codewords. The multi-channel decoder circuit further comprises a distribution controller circuit configured to distribute each incoming codeword of the one or more codewords to the respective unit decoder circuit of the set of unit decoder circuits within the distributed decoder circuit, based on determining a currently available unit decoder circuit within the set of unit decoder circuits.Type: GrantFiled: November 20, 2018Date of Patent: November 14, 2023Assignee: MaxLinear, Inc.Inventors: Gert Schedelbeck, Stefan Uhlemann
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Patent number: 11797396Abstract: An error recovery process provides for selecting a first recovery scheme for a decoding attempt on a first subset of a set of failed data blocks read from a data track; selecting a second different recovery scheme for a decoding attempt on a second subset of the set of failed data blocks read from the data track; and during a single revolution of the data track, performing operations to decode a first subset of the failed data blocks according to the first recovery scheme operations to decode the second subset of the failed data blocks according to the second different recovery scheme.Type: GrantFiled: July 30, 2020Date of Patent: October 24, 2023Assignee: SEAGATE TECHNOLOGY LLCInventors: Deepak Sridhara, Jason Bellorado, Ara Patapoutian, Marcus Marrow
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Patent number: 11784756Abstract: A memory access technology and a computer system, where the computer system includes a memory controller and a medium controller connected to the memory controller. In the computer system, when detecting that an error occurs in first data that is returned by the medium controller in response to a first send command, the memory controller determines sequence information of the first send command in a plurality of send commands that have been sent by the memory controller within a time period from a time point at which the first send command is sent to a current time, and sends a data retransmission command to the medium controller to instruct the medium controller to resend the first data based on the sequence information.Type: GrantFiled: June 5, 2020Date of Patent: October 10, 2023Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Shihai Xiao, Florian Longnos, Feng Yang
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Patent number: 11750334Abstract: The data collection management device (10) is connected via a network to a plurality of communication devices (20) performing cyclic communication and includes: a network configuration storage (17) to store network configuration information indicating the communication devices participating in the cyclic communication; a data receiving unit (11) to receive communication data multicast from each communication device (20); a received data storage (12) to store the received communication data as collected data; a received data determination unit (13) to determine whether there is missing data in the collected data and identify unreceived communication data, based on information specifying communication cycles included in the collected data, on information specifying sender communication devices included in the collected data, and on network configuration information; and a retransmission requesting unit (15) to transmit a retransmission request of the unreceived communication data to one of the plurality of commType: GrantFiled: December 25, 2019Date of Patent: September 5, 2023Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Yuki Nakano
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Patent number: 11719747Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.Type: GrantFiled: June 3, 2021Date of Patent: August 8, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Joon-Won Ko
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Patent number: 11715543Abstract: A memory test circuit apparatus and a method are provided. The method may include: compressing first test data output by a first storage array in a memory to generate first compressed data, compressing second test data output by a second storage array in the memory to generate second compressed data, compressing the first compressed data and the second compressed data to generate third compressed data, and outputting one of the first compressed data, the second compressed data and the third compressed data to determine a working condition of each of the first storage array and the second storage array. This method can provide not only a test result on a memory, but also a test result for individual storage array within the memory, which improves the efficiency of a circuit test.Type: GrantFiled: December 16, 2020Date of Patent: August 1, 2023Assignee: Changxin Memory Technologies, Inc.Inventor: Cheng-Jer Yang
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Patent number: 11710530Abstract: The present disclosure provides a memory device, wherein: an address latch can output a block selection control signal according to a block selection enable signal; a test mode selection unit can output a test mode selection signal according to a test mode selection instruction signal; a block selection unit outputs a block selection signal according to a mode selection signal and a block selection enable signal; when the memory enters a first test mode according to the test mode selection signal, an output buffer disables some of the input/output ports, and sequentially outputs the first input/output data and the second input/output data through un-disabled the input/output ports. The memory device according to the present disclosure can occupy less input/output ports of a test machine.Type: GrantFiled: August 24, 2020Date of Patent: July 25, 2023Assignee: Changxin Memory Technologies, Inc.Inventor: Shu-Liang Ning
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Patent number: 11663077Abstract: Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.Type: GrantFiled: June 23, 2020Date of Patent: May 30, 2023Assignee: Western Digital Technologies, Inc.Inventor: Minghai Qin
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Patent number: 11632135Abstract: An example methods for interleaved BCH codes can include encoding a plurality of portions of data using a first generator polynomial to obtain a plurality of respective BCH codewords. The method can include encoding an additional BCH codeword based at least in part on a second plurality of portions of data and the plurality of BCH codewords using a second generator polynomial. The method can include outputting the plurality of respective BCH codewords and the additional BCH codeword.Type: GrantFiled: May 17, 2019Date of Patent: April 18, 2023Assignee: Micron Technology, Inc.Inventor: Yingquan Wu
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Patent number: 11616600Abstract: An apparatus for generating broadcast signal frame according to an embodiment of the present invention includes a combiner configured to generate a multiplexed signal by combining a core layer signal and an enhanced layer signal at different power levels; a power normalizer configured to reduce the power of the multiplexed signal to a power level corresponding to the core layer signal; a time interleaver configured to generate a time -interleaved signal by performing interleaving that is applied to both the core layer signal and the enhanced layer signal; and a frame builder configured to generate a broadcast signal frame including a preamble for signaling time interleaver information corresponding to the time interleaver, the time interleaver uses one of time interleaver groups, and a boundary between the time interleaver groups is a boundary between Physical Layer Pipes (PLPs) of a core layer corresponding to the core layer signal.Type: GrantFiled: November 15, 2021Date of Patent: March 28, 2023Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTEInventors: Sun-Hyoung Kwon, Jae-Young Lee, Sung-Ik Park, Bo-Mi Lim, Heung-Mook Kim, Jin-Hyuk Song
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Patent number: 11601139Abstract: Methods, apparatus, systems and articles of manufacture to determine and apply polarity-based error correction code are disclosed. In some examples, the methods and apparatus create an array by setting a first set of bit locations of a code word to have a first value and setting a second set of bit locations of the code word to have a second value different from the first value. In some examples, when the array satisfies a parity check, the methods and apparatus determine that bit locations having the first value from the array form a polarity-based error correction code.Type: GrantFiled: November 12, 2019Date of Patent: March 7, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manish Goel, Yuming Zhu
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Patent number: 11601142Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.Type: GrantFiled: March 5, 2021Date of Patent: March 7, 2023Assignee: Saturn Licensing LLCInventors: Ryoji Ikegaya, Makiko Yamamoto, Yuji Shinohara