Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

Abstract: Various implementations described herein are directed to technologies for providing error detection for a disk drive of a digital video recorder (DVR). Access data is measured according to a degree of usage of a disk drive of a DVR. The access data is stored. The stored access data is analyzed to detect performance degradation of the disk drive.

Abstract: A transmitter is provided. The transmitter includes: an outer encoder configured to encode input bits to generate outer-encoded bits including the input bits and parity bits; a zero padder configured to generate a plurality of bit groups each of which is formed of a same number of bits, maps the outer-encoded bits to some of the bits in the bit groups, and pads zero bits to remaining bits in the bit groups, based on a predetermined shortening pattern, thereby to constitute Low Density Parity Check (LDPC) information bits; and an LDPC encoder configured to encode the LDPC information bits, wherein the remaining bits in which zero bits are padded include some of the bit groups which are not sequentially disposed in the LDPC information bits.

Abstract: Systems and methods for correcting corrupted network packets are provided. An example method includes receiving a network packet via a communication channel. The network packet includes a payload and a Cyclic Redundancy Check (CRC) associated with the payload. The method continues with calculating a reference CRC based on the received payload and determining, based on the reference CRC and the received CRC, whether the network packet is corrupted. Based on the determination that the network packet is corrupted, the method continues with selecting a predetermined number of positions of bits in the payload of the network packet, precalculating a set of additional CRCs, and determining, based on the reference CRC and the set of additional CRCs, a combination of bit flips at the predetermined number of positions. The method also includes modifying the payload according to the combination of bit flips at the predetermined number of positions.

Abstract: A memory with an error correction function includes a controller and a memory cell array. The controller optionally writes written data to a normal storage area and a backup area of the memory cell array, and when the controller reads first data corresponding to the written data from the normal storage area, if at least two errors are included in the first data, the controller reads the backup area to output second data corresponding to the written data from the backup area.

Abstract: Systems and methods for error correction in network packets are provided. An example method includes receiving a network packet via a communication channel, the network packet including a content and an error-detecting code associated with the content, determining, based on the error-detecting code, that the network packet is corrupted, selecting a pre-determined number of positions of bits in the content of the network packet, changing values of the bits in the selected positions to a bit value combination selected from all possible bit value combinations in the selected positions to modify the content and calculating a further error-detecting code of the modified content until the further error-detecting code of the modified payload matches the error-detecting code received via the communication channel or all possible bit combinations have been selected, and if the further error-detecting code does not match the error-detecting code, requesting for retransmission of the network packet.

Abstract: A device includes a plurality of memory cells, an error detection circuit configured to detect at least one memory cell storing error data and a refresh control circuit including a register configured to store an error address corresponding to the at least one memory cell storing error data. The refresh control circuit is configured to control a refresh cycle of the error address.

Abstract: A memory device, memory address decoder, a memory system and related method for memory attack detection are disclosed. An apparatus includes a memory decoder include multiple stages in a decoding path configured to generate a select signal from an input address signal, and fault detecting logic operably coupled with the memory decoder and configured to receive feedback signals distributed from the multiple stages indicative of a fault along the decoding path.

Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.

Abstract: Codewords of an error correcting code can be received. The codewords can be separated into multiple segments. The segments of the codewords can be distributed in an error correcting layout across a plurality of dies where at least a portion of the error correcting layout constitutes a Latin Square (LS) layout.

Abstract: Aspects of the present disclosure provide techniques for physical broadcast channel (PBCH) and master information block (MIB) design. An example method is provided for operations which may be performed by a user equipment (UE). The example method generally comprises receiving, a first number of symbols within a first subframe on a physical channel, performing a first blind decode on the first number of symbols to obtain a first set of bits, performing one or more cyclic shifts on the first set of bits, calculating a redundancy check value for the first set of bits, and decoding an information block based on the whether the redundancy check value passes. Aspects of the present disclosure provide techniques for transmission configurations. An example method is provided for operations which may be performed by a base station (BS).

Abstract: Various embodiments disclosed herein provide for a transmission system using codeblock segmentation that does not have to retransmit each of the codeblock segments if one of the codeblock segments is determined to have an error at the receiver. The transmitter segments a transport block into a group of codeblock segments, each having respective cyclic redundancy check bits. The receiver receives the group of codeblock segments, and during decoding, if it is determined that one of the segments have an error, instead of just sending back to the transmitter a negative acknowledgement (NAK) the receiver can send back a NAK as well as an indicator of which segment was in error. The transmitter can then resend just the segment in error in order to improve efficiency and decrease power requirements.

Abstract: A reception apparatus includes a receiver and circuitry. The receiver receives, from a transmission apparatus, a plurality of packets that include code word symbols which include an information word symbol and a parity symbol. The information word symbol is generated from transmission information. The parity symbol is calculated from the information word symbols. The circuitry decodes the code word symbols that are included in the plurality of packets. The number of first packets and the number of second packets among the plurality of packets are shared between the transmission apparatus and the reception apparatus. Each of the first packets includes the information word symbol. Each of the second packets includes the parity symbol.

Abstract: A semiconductor device comprises a data region including a plurality of first semiconductor chips and configured to store data requested by a host, and a metadata region including one or more second semiconductor chips and configured to store metadata corresponding to the plurality of first semiconductor chips in the data region. The data region and the metadata region are accessed using different signals to perform a command-based operation corresponding to a command signal.

Abstract: The present invention provides an encoder built-in self-test (BIST) circuit applied in a flash memory controller, wherein the encoder BIST circuit includes a control circuit and an encoder. In operations of the encoder BIST circuit, without accessing any flash memory, the control circuit generates input data to the encoder, and the encoder encodes the input data to generate a check code to the control circuit, wherein the check code is arranged to determine whether functions of the encoder fail or not.

Abstract: A method employed in a low-density parity-check code decoder includes: receiving a specific data portion of a first codeword; calculating a flipping function value of the specific data portion of the first codeword according to the specific data portion by using checking equations of a parity check matrix to calculate checking values of the specific data portion; and determining whether to flip the specific data portion of the first codeword by comparing the flipping function value with a flipping threshold which has been calculated based on a plurality of flipping function values of a plurality of previous data portions earlier than the specific data portion.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a memory controller. Each of first storage regions of each of the nonvolatile memory includes a plurality of second storage regions. Each of pieces of first data includes pieces of second data as storage target data. Third data includes pieces of the second data that are selected one by one from each of the pieces of first data. The memory controller executes first decoding of decoding each of the pieces of first data on the basis of a first error correcting code generated by using the first data, and executes second decoding of decoding the third data including a bit of which reliability, which relates to each bit in each of the second storage regions that fail in the first decoding, is less than reliability of other bits on the basis of a second error correcting code.

Abstract: Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.

Abstract: An apparatus and method for broadcast signal frame using a boundary between Physical Layer Pipes (PLPs) of a core layer are disclosed.

Abstract: Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator, includes: a PUF cell array comprising a plurality of bit cells configured in at least one column and at least one row, wherein the plurality of bit cells each provides two voltage transient behaviors on two corresponding bit lines of the at least one column; and at least two load control circuits coupled to the two bit lines of the at least one corresponding column, wherein the at least two load control circuits are each configured to provide at least one discharge pathway to at least one of the two corresponding bit lines, wherein the at least one discharge pathway is configured to change at least one of the two voltage transient behaviors so as to determine stability of each of the plurality of bit cells of the PUF cell array.