Abstract: An Ethernet transceiver is disclosed. The Ethernet transceiver includes transmit circuitry having a forward error correction (FEC) encoder to encode data into FEC frames. A modulator modulates the FEC frames into symbols. A precoder equalizes the symbols and a transmitter transmits the equalized symbols over a reduced number of channels NS with respect to a baseline number of channels N0. For a reduced data rate BS with respect to a baseline data rate B0, the FEC frames are assembled by the FEC encoder to exhibit an expanded frame time FTS that is expanded from a baseline frame time FT0 by a factor of B0/BS. The modulator generates symbols that are transmitted by the transmit circuit at a symbol rate SRS that is reduced from a baseline symbol rate SR0 by a factor of (B0*NS)/(BS*N0).

Abstract: A decoding method is provided, and the method includes performing a decoding operation on a plurality of data bit value sets of a codeword. The decoding operation includes following steps: (1) obtaining a syndrome of the data bit value sets; (2) determining whether the codeword is correct or incorrect according to the latest obtained syndrome, wherein if the codeword is correct, the decoding operation is ended, wherein if the codeword is wrong, continuing to step (3) to start an iterative operation; (3) obtaining a plurality of error value sets respectively corresponding to the data bit value sets, wherein in response to obtaining a first error value set, steps (4) and (5) are performed simultaneously; (4) performing an extreme value search operation; (5) performing a bit-flipping operation; and (6) performing a syndrome calculation operation after the step (5) is completed, and performing step (2).

Abstract: A method of optimizing a read threshold voltage shift value for non-volatile memory units organized as memory pages may be provided. An ECC check is performed for active page reads. The method comprises, as part of the read operation, determining a status of the memory page, and reading a memory page with a current threshold voltage shift (TVS) value. Additionally, the method comprises, upon determining that a read memory page command passed an ECC check, returning corrected data read, and upon determining that the read memory page did not pass the ECC check, adjusting the current TVS value based on the status of the memory page to be read. Furthermore, the method comprises, while the read memory pages continues to not pass the ECC check, repeating the adjusting the current TVS value and the determining that the read memory page passes ECC check until a stop condition is met.

Abstract: A memory device having an error correction function includes: a memory element including multiple memory cells, a reconfiguration logic unit configured to group input data according to data retention properties of each memory cell in which each of the input data will be stored or group storage data stored in the memory element according to data retention properties of each memory cell in which each of the storage data is stored and arrange each of the input data or each of the storage data grouped by identical retention properties to be adjacent to each other, an error correction encoder configured to apply an error correction encoding algorithm with a different intensity to the grouped input data in each group, and an error correction decoder configured to apply an error correction decoding algorithm corresponding to an intensity applied by the error correction encoder to the grouped storage data in each group.

Abstract: A decoding circuit includes a Bose-Chaudhuri-Hocquenghem (BCH) decoder. The BCH decoder includes a Syndrome stage for generating syndromes based on a BCH encoded word, a Berlekamp-Massey (BM) stage performing a Berlekamp-Massey algorithm on the syndromes to generate Error Location Polynomial (ELP) coefficients, a Chien stage that performs a Chien search on the ELP coefficients using a Fast Fourier Transform (FFT) to generate error bits and iteration information, and a Frame Fixer stage configured to reorder the error bits to be sequential based on the iteration information. The BCH decoder decodes the BCH encoded word using the reordered error bits.

Abstract: A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.

Abstract: Methods, systems, and devices for wireless communications are described. A wireless device, such as a user equipment (UE) may monitor for a decoding candidate of a codeword, wherein the codeword corresponds to a set of received bit metrics, and the decoding candidate corresponds to a plurality of information bits encoded using a polar code, determine a composite detection metric for the codeword for the decoding candidate, where the composite detection metric is derived from a subset of bit metrics for an intermediate polarization layer of the polar code, and determine a classification for performing a list decoding process on the codeword according to the decoding candidate based at least in part on the composite detection metric.

Abstract: Methods, apparatuses, and system for performing at least one of error correction or error detection are described. In one embodiment, a radio frequency identification (RFID) tag receives a signal activating or interrogating the tag. The tag includes memory that stores data associated with the tag. The tag performs at least one of error detection or error correction on the stored data. The error detection includes detecting, by the tag, that one or more bits of the stored data are inflicted with an error. The error correction includes correcting the erroneous bit if the error affects less than a predetermined number of the bits of the stored data. The tag transmits the stored data to a reader in response to the detection or correction. The reader can analyze the stored data for additional information about the error or provide the stored data to another computing system that performs the analysis.

Abstract: An embedded logic analyzer of an integrated circuit includes a comparison block configured to generate a capture data signal and a plurality of comparison enable signals based on an input data signal from one of function blocks included in the integrated circuit such that the comparison enable signals are activated respectively based on different comparison conditions; an operation block configured to perform a logic operation on the comparison enable signals to generate a data enable signal indicating a data capture timing; and packer circuitry configured to generate a packer data signal including capture data and capture time information based on the capture data signal, the data enable signal and a time information signal.

Abstract: Technology is disclosed for reading non-volatile memory when a host does not need perfect data. By allowing the memory to return data with some errors, the data will be provided to the host much quicker. Therefore, in response to one or more host read commands, the memory system returns multiple copies of the data over time, progressively getting better so that later in time copies of the data have lower number of errors. The host decides when the error rate is good enough and stops the process (or ignores the rest of the results).

Abstract: The present technology relates to a data processing device and a data processing method which can ensure high communication quality in data transmission using LDPC codes. In group-wise interleaving, an LDPC code having a code length N of 64800 bits and a coding rate r of 11/15 is interleaved in a unit of a bit group of 360 bits. In group-wise deinterleaving, a sequence of bit groups of the LDPC code which has been subjected to the group-wise interleaving is returned to an original sequence. The present technology can be applied to, for example, a case in which data transmission is performed using LDPC codes.

Abstract: A computer device comprises a first processor; a plurality of memory circuits, a first one of which comprises one or more other processors; a data bus coupling the first processor to each of the memory circuits, each of the memory circuits having a data port with a width of m bits and the data bus having a width of n bits, n being higher than m, the first processor and/or another circuit being suitable for reading or writing the data value of n bits in the first memory circuit by converting a first address into a plurality of second addresses corresponding to memory locations of m bits in the first memory circuit, and by performing the reading or writing operation of the data value of n bits in the first memory circuit over a plurality of memory access operations.

Abstract: In this specification, a method of performing a hybrid automatic request (HARQ) in a wireless communication system is performed by a user equipment, and includes receiving first data from a first eNB through a first radio link; receiving second data from at least one second eNB through a second radio link; combining the first data and the second data; decoding the combined data; and feedbacking the results of the decoding through at least one of the first radio link or the second radio link.

Abstract: A memory controller includes a memory to store results of a reference performance test (RT) performed on a non-volatile memory (NVM) die, where the results of the RT include one or more first indicators of failure associated with one or more first read/write cycles of the NVM die before the NVM die is placed in use. The memory controller further includes an analyzer coupled with the memory to perform, in one or more second read/write cycles, one or more field tests that provide second indicators of failure associated with one or more second read/write cycles of the NVM die during the use of the NVM die, and further to predict and dynamically adjust, over one or more second read/write cycles, at least one of likelihood or expected time of failure of the NVM, based at least in part on the first and second indicators of failure.

Abstract: An optical receiver is configured to receive optical signals representative of digital information over an optical communication link. The optical receiver is further configured to decode symbol estimates from an optical signal received over the optical communication link; to demap first bit estimates and second bit estimates from the symbol estimates; to decode third bit estimates from the first bit estimates using second FEC decoding of a second FEC scheme; and to decode fourth bit estimates from both the second bit estimates and the third bit estimates using first FEC decoding of a first FEC scheme. The optical receiver is further configured to use one or more of the third bit estimates to demap one or more of the second bit estimates. Concatenation of the first and second FEC schemes as described herein may relax design constraints on the second FEC scheme, which may reduce power consumption and design complexity.

Abstract: In one general embodiment, a method includes receiving data logically organized into a predetermined number of two-dimensional arrays, each two-dimensional array including a plurality of NS codewords positioned orthogonally to a plurality of WS codewords. The method also includes successively writing each of the NS codewords to a data storage medium. A first NS codeword from a first two-dimensional array is written to the data storage medium prior to starting to write a second NS codeword from the first two-dimensional array. Also, the plurality of NS codewords are protected with a stronger encoding than the plurality of WS codewords.

Abstract: The present specification provides a method for performing a physical layer security-based hybrid automatic repeat request (HARQ). The method comprises the steps of: generating a first code comprising information bits for forming data to be transmitted, and non-information bits which are unrelated to the data to be transmitted; generating a second code, having a length which differs from that of the first code, by puncturing the first code; determining locations of the information bits and non-information bits within the second code such that a variance of mutual information for each of the information bits and the non-information bits is maximized; and performing the HARQ by using the second code in which the locations of the information bits and the non-information bits are determined.

Abstract: Disclosed is a method of operating a storage device including a NAND flash memory including memory cells grouped into blocks, each block being divided into pages. According to the method, a controller in the storage device loads, onto a memory region, a look-up table containing first read reference voltage sets corresponding to respective retention degradation stages of the NAND flash memory and second read reference voltages sets corresponding to respective pages which vary in terms of the threshold voltages. Subsequently, the controller performs a read operation on the memory cells on a per-block basis by using the first read reference voltage set corresponding to a current retention degradation stage, the second read reference voltage set corresponding to a current page, or both, until all of the memory cells in a current block are correctly read.

Abstract: A construction method for a (n,n(n?1),n?1) permutation group code based on coset partition is provided. The presented (n,n(n?1),n?1) permutation group code has an error-correcting capability of d?1 and features a strong anti-interference capability for channel interferences comprising multi-frequency interferences and signal fading. As n is a prime, for a permutation code family with a minimum distance of n?1 and a code set size of n(n?1), the invention provides a method of calculating n?1 orbit leader permutation codewords by On={?o1}?=1n-1(mod n) and enumerating residual codewords of the code set by Pn=CnOn={(l1)n-1On}={(rn)n-1On}. Besides, a generator of the code set thereof is provided. The (n,n(n?1),n?1) permutation group code of the invention is an algebraic-structured code, n?1 codewords of the orbit leader array can be obtained simply by adder and (mod n) calculator rather than multiplication of positive integers.

Abstract: Systems and methods presented herein provide for testing degradation in a storage device. In one embodiment, a storage controller is operable to test individual portions of a first of the plurality of storage areas of the storage device by: analyzing individual portions of the first storage area; determining that one or more of the individual portions of the first storage area have failed; and retire the failed one or more portions of the first storage area. The storage controller is further operable to write to the first storage area using an error correction code (ECC), and to test the remaining portions of the first storage area to determine whether the first storage area should be retired in response to writing to the first storage area.