Abstract: Techniques are disclosed relating to configuring an interlock memory system. In one embodiment, a method includes determining a sequence of memory access requests for a program and generating information specifying memory access constraints based on the sequence of memory accesses, where the information is usable to avoid memory access hazards for the sequence of memory accesses. In this embodiment, the method further includes configuring first circuitry using the information, where the first circuitry is included in or coupled to a memory. In this embodiment, after the configuring, the first circuitry is operable to perform memory access requests to the memory corresponding to the sequence of memory accesses while avoiding the memory access hazards, without receiving other information indicating the memory access hazards.

Abstract: In one aspect, a pipelined ECC-protected cache access method and apparatus provides that during a normal operating mode, for a given cache transaction, a tag comparison action and a data RAM read are performed speculatively in a time during which an ECC calculation occurs. If a correctable error occurs, the tag comparison action and data RAM are repeated and an error mode is entered. Subsequent transactions are processed by performing the ECC calculation, without concurrent speculative actions, and a tag comparison and read are performed using only the tag data available after the ECC calculation. A reset to normal mode is effected by detecting a gap between transactions that is sufficient to avoid a conflict for use of tag comparison circuitry for an earlier transaction having a repeated tag comparison and a later transaction having a speculative tag comparison.

Abstract: A storage apparatus includes a channel control unit, a storage device, and a processor. The channel control unit includes a plurality of operation units. The processor specifies, when receiving a request for read of a plurality of pieces of element data from a host computer, the plurality of pieces of element data to the plurality of operation units, respectively. The plurality of operation units respectively reads the plurality of pieces of element data from the storage device, calculates a plurality of partial codes that is a plurality of guarantee codes on the basis of the plurality of pieces of element data, and transmits the plurality of partial codes to the processor. The processor calculates, on the basis of the plurality of partial codes, a sequence code that is a guarantee code of sequence data including the plurality of pieces of element data which is concatenated.

Abstract: Various aspects of the disclose techniques relate to techniques of testing interconnects in stacked designs. A single-pulse signal, generated by a first circuit state element on a first die, is applied to a first end of an interconnect and captured at a second end of the interconnect using a clock port of a second circuit state element on a second die. A faulty interconnect may cause the single-pulse signal too distorted to reach the threshold voltage of the second circuit element.

Abstract: Technologies are generally described for partial cloud data storage. In one example, a method includes dividing, by a system comprising a processor, a file into a set of source packets in response to an indication that the file is to be stored in a data store of a network device. The method also includes transforming the set of source packets into a set of encoded packets by encoding the set of packets into codeword symbols of an error correcting code. Further, the method includes facilitating storage of a first portion of the set of encoded packets to the data store of the network device and a second portion of the set of encoded packets to one or more user devices. A first number of packets in the first portion is more than a second number of packets in the second portion and the second portion is at least used to decode the file.

Abstract: The invention provides a method for launch-off-shift at-speed scan testing for at least two scan chains of an integrated circuit comprises iteratively shifting set values for functional elements of a first one of the scan chains clocked with a shift clock, iteratively shifting set values for functional elements of a second one of the scan chains clocked with the shift clock, launching an at-speed scan test clocked with a functional clock for the first one of the scan chains at a last shift cycle of the first one of the scan chains, delaying the last shift cycle for the second one of the scan chains for a predetermined time span, launching an at-speed scan test clocked with a functional clock for the second one of the scan chains at the last shift cycle of the second one of the scan chains, capturing the sample values of the functional elements of the first and second scan chains after the last shift cycle of the scan chains.

Abstract: Certain example embodiments relate to a complex event processing, CEP, system, including an error correction component configured to receive a stream of events including at least one event from at least one event source. The error correction component is configured to detect at least one error in the at least one event. The error correction component is configured to emit a corrected stream of events including at least one event, which can then be processed by at least one event processing application.

Abstract: The present invention provides systems and methods to detect when hard decisions change for bit nodes of one or more layers of a layered LDPC decoder and to update accumulated partial syndrome calculations for those layers. As hard decisions of bit nodes are generated, they are compared with their previous values. If the hard decisions change, partial syndrome calculations are accumulated and updated for the layers having non-zero elements in one or more columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions. If the hard decisions for the bit nodes are unchanged, the partial syndrome calculations for the corresponding layers are not updated. Changes to hard decisions of codewords are tracked and partial syndromes are flipped for the layers of the columns of the parity check matrix corresponding to the bit nodes of the changed hard decisions.

Abstract: A method is provided for controlling a redundant array of independent disks (RAID). The method comprises a computer system writing data to a RAID and reading data from the RAID, wherein the RAID includes a controller and a plurality of data storage devices, including a flash data storage device. The method further comprises the controller detecting whether or not the flash data storage device is in read-only mode, and the controller preventing attempts to write data to the flash data storage device in response to detecting that the flash data storage device is in read-only mode. Optionally, when the flash data storage device is in read-only mode, the controller may redirect writes intended for the flash data storage device to empty data storage space on another data storage device or cache memory, or modify the parity stripe of a major stripe in view of the data intended to be written.

Abstract: A bit coding device that creates a coded bit sequence by performing error correction coding on an input bit sequence that is input, includes a coding unit that creates a first bit sequence by performing the error correction coding on the input bit sequence, an extraction unit that extracts a second bit sequence from the first bit sequence, and an information compression unit that creates a third bit sequence by performing lossy compression on the second bit sequence, in which coded bits include at least a portion of the third bit sequence.

Abstract: In one embodiment, a system includes a data processing unit configured to read encoded data from a magnetic tape medium. The data processing unit is also configured to decode a plurality of codeword interleaves (CWIs) from the encoded data, each CWI being a row in a sub data set logically organized into a two-dimensional array. The array includes a predetermined number of rows and columns of predetermined lengths. The data processing unit is also configured to determine an address for a first-written CWI without successfully decoding a corresponding codeword interleave designation (CWID) from the encoded data, each CWID specifying an address for a corresponding CWI. Also, each CWID is calculated as a function of a logical track number and a CWI set number.

Abstract: An integrated circuit includes a substrate, a master system on the substrate, a slave system on the substrate that is coupled to communicate with the master system, a first clock signal coupled to the master system, and a second clock signal coupled to the slave system. The master system is configured to isolate the slave system from the master system while a first test of the master system is conducted in parallel with a second test of the slave system. The master system uses the first clock signal during the first test and the slave system uses the second clock signal during the second test.

Abstract: A method for performing scan testing using a scan chain having a plurality of storage elements is described. During a capture phase, each storage element of the scan chain stores data from a first data input of the storage element synchronously to a clock signal. And during a shift phase, a scan pattern is shifted into the scan chain in which each storage element stores data from a second data input of the storage element asynchronously with to the clock signal.

Abstract: In an embodiment, a memory interface includes integrated circuitry to verify the integrity of the memory interface. The circuitry propagates a test pattern through different paths of the memory interface, and checks the result against a reference value to determine whether the components of the paths are operating within an acceptable tolerance. The memory interface can also communicate with ATE to initiate such tests and return the results to the ATE.