Abstract: Disclosure is related to a method and a system for intelligent defect classification and sampling, and a computer-readable storage device. The computer-implemented method acquires in-line defect inspection file, and retrieves the defect patterns over a device under test, e.g. a wafer from a fab. The system incorporates a defect pattern recognition engine to recognize the defect signature patterns from the defect patterns. A sampling scheme is performed to acquire weak defect patterns. A critical area analysis based on failure probability of weak patterns is incorporated to performing the sampling. The defect layout pattern groups probably causing the open or short failure can be obtained. The defect signature patterns through sampling are then displayed using a browsing system. Through a user interface, the user can perform functions, such as filtering, selection and merging, onto the defect patterns.

Abstract: An apparatus for performing scan test of IC chip includes a shift-frequency searching unit that searches usable shift frequency for a target scan section among at least one scan section each including whole or part of at least one scan pattern inputted to a scan path. When searching usable shift frequency for the target scan section, the shift-frequency searching unit scales shift frequency of the target scan section differently from that of at least one scan section among scan sections shifted before or after the target scan section or sets shift frequency of the target scan section differently from that of the at least one scan section among the scan sections shifted before or after the target scan section, and searches shift frequency with which result of the scan test indicates pass or shift frequency with which result of the scan test indicates fail.

Abstract: A construction method for a (n,n(n?1),n?1) permutation group code based on coset partition is provided. The presented (n,n(n?1),n?1) permutation group code has an error-correcting capability of d?1 and features a strong anti-interference capability for channel interferences comprising multi-frequency interferences and signal fading. As n is a prime, for a permutation code family with a minimum distance of n?1 and a code set size of n(n?1), the invention provides a method of calculating n?1 orbit leader permutation codewords by On={?o1}?=1n?1(mod n) and enumerating residual codewords of the code set by Pn=CnOn={(l1)n?1On}={(rn)n?1On)}. Besides, a generator of the code set thereof is provided. The (n,n(n?1),n?1) permutation group code of the invention is an algebraic-structured code, n?1 codewords of the orbit leader array can be obtained simply by adder and (mod n) calculator rather than multiplication of positive integers.

Abstract: In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

Abstract: Modern communication systems must cope with varying channel conditions and differing throughput constraints. Polar codes despite being the first error-correcting codes with an explicit construction to achieve the symmetric capacity of memoryless channels are not currently employed against other older coding protocols such as low-density parity check (LDPC) codes as their performance at short/moderate lengths has been inferior and their decoding algorithm is serial leading to low decoding throughput. Accordingly techniques to address these issues are identified and disclosed including decoders that decode constituent codes without recursion and/or recognize classes of constituent directly decodable codes thereby increasing the decoder throughput. Flexible encoders and decoders supporting polar codes of any length up to a design maximum allow adaptive polar code systems responsive to communication link characteristics, performance, etc. while maximizing throughput.

Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.

Abstract: Systems and methods are provided herein for removing the need to account for varying lengths of data packets that are transmitted during a single clock cycle, and to require only one CRC calculation block for handling parallel processing of a stream of data packets received during a clock cycle. Moreover, systems and methods are provided herein for eliminating a need for a shifter, such as a barrel shifter, to process the data packets of a single clock cycle in parallel.

Abstract: A method, circuit, and design structure for an on-chip sequence profiler involves a programmable matrix and FSM in a logic circuit, a first latch receiving a scan path bit sequence and a first clock signal and generating a first output to control a select input of a first multiplexer, a first multiplexer selecting among functional path bit sequences and outputting a bit sequence to a second latch, a second latch receiving the bit sequence from the first multiplexer and a second clock signal via a second multiplexer and outputting a bit sequence to a logic circuit, a logic circuit receiving the bit sequence from the second latch and outputting a clock control signal to the clock and a second selector control signal to the second multiplexer, and a second multiplexer receiving a second clock signal from the clock and outputting the second clock signal to the second latch.

Abstract: An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.

Abstract: Exemplary methods, apparatuses, and systems include a first layer of a virtual storage area network (VSAN) module receiving a write request from a data compute node. The write request includes data to be written and the VSAN module is distributed across a plurality of computers to provide an aggregate object store using storage attached to each of the plurality of computers. The first layer of the VSAN module calculates a checksum for the data to be written and passes the data to be written and the checksum to a second layer of the VSAN module. The second layer of the VSAN module calculates a first verification checksum for the data to be written. The data and the checksum are written to persistent storage in response to determining the first verification checksum matches the checksum passed by the first layer of the VSAN module.

Abstract: Techniques for interleaving information for media data are described. In at least some embodiments, interleaving information is propagated from a network-based service to endpoint devices that participate in communication sessions. The endpoint devices may utilize the interleaving information to interleave media data of communication sessions.

Abstract: Techniques are disclosed relating to resolving memory access hazards. In one embodiment, an apparatus includes a memory and circuitry coupled to or comprised in the memory. In this embodiment, the circuitry is configured to receive a sequence of memory access requests for the memory, where the sequence of memory access requests is configured to access locations associated with entries in a matrix. In this embodiment, the circuitry is configured with memory access constraints for the sequence of memory access requests. In this embodiment, the circuitry is configured to grant the sequence of memory access requests subject to the memory access constraints, thereby avoiding memory access hazards for a sequence of memory accesses corresponding to the sequence of memory access requests.

Abstract: Exemplary methods, apparatuses, and systems maintain hole boundary information by calculating a block attribute parity value. For example, a request is received to write to a first block of a stripe of data. A block attribute of a second block is determined. The block attribute of the second block indicates whether the second block includes written data or is a hole. A block attribute parity value is calculated based upon both the block attribute of the first block and the block attribute of the second block. The block attribute of the first block indicates the first block includes written data based upon the received request. The block attribute parity value and the data parity value are stored on one of the physical storage devices in response to the received write request. As a result, if a disk is lost, holes can be recovered using the block attribute parity value.

Abstract: A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

Abstract: A method and apparatus for reducing memory built-in self-test (MBIST) area by optimizing the number of interfaces required for testing a given set of memories is provided. The method begins when memories of a same configuration are grouped together. One memory is then selected from each of the groups. MBIST insertion is then performed for a selected group of memories, and the selected group of memories contains memories of different configurations. Control logic is used to select each group of memories separately. The memory group under test may also be selected using programmable user bits. An apparatus is also provided. The apparatus includes: a controller, at least one memory interface in communication with the controller, at least one control logic cloud in communication with the at least one memory interface; and at least one bit bus.

Abstract: An image forming device that includes a communication device includes a class judging unit, a number-of-times determination unit, and a retry execution unit. The communication device transmits data to a management device through a first communication network provided by a communication carrier. The class judging unit judges a class under which a first error having occurred in data transmission falls, the class being predetermined according to a probability of a successful transmission retry. The number-of-times determination unit determines the number of times a retry is performed in response to the first error, such that the number of times the retry is performed is decreased as the probability of a successful transmission retry becomes low. The retry execution unit causes the communication device to execute the retry in response to the first error the determined number of times.

Abstract: The effects of decoherence and/or noise in adiabatic quantum computation and quantum annealing are reduced by implementing replica coding schemes. Multiple instances of the same problem are mapped to respective subsets of the qubits and coupling devices of a quantum processor. The multiple instances are evolved simultaneously in the presence of coupling between the qubits of different instances. Quantum processor architectures that are adapted to facilitate replica coding are also described.

Abstract: On-chip field testing methods and apparatus are disclosed. Example on-chip testers disclosed herein include a decoder having a test data input and a test stimuli interface. Disclosed example on-chip testers also include a multiplexer having a first multiplexer interface coupled to the test stimuli interface, a second multiplexer interface coupled to an automatic test equipment interface, a third multiplexer interface coupled to a design-for-testing subsystem interface and an interface selection input. Disclosed example on-chip testers further include a memory having a memory interface coupled to the test data input.

Abstract: An integrated circuit (IC) includes a logic built-in self-test (LBIST) system that includes scan chains. The scan chains receive a clock signal and test pattern signals, and generate scan out signals. A debug controller receives the scan out signals and shifts a set of the scan out signals to a joint test action group (JTAG) controller. The debug controller also maintains a dynamic count indicative of the number of debug shift operations performed, and compares the dynamic count with a final count. If the dynamic count is less than the final count, the debug controller performs a second debug shift operation, which facilitates determination of a fault location in the IC.

Abstract: A debug circuit, includes: a controller to start a debugging of a circuit based on first and second code values, the first code value obtained by encoding a first sequence included in a processing sequence indicating a condition for a process of the circuit, the second code value obtained by encoding a second sequence subsequent to the first sequence, wherein the controller performs to: calculate a third code value as a current code value based on signals input and output to the circuit; output, as a fourth code value, a previous third code value that is earlier than the current code value; detect the first sequence by comparing a difference between the third code value and the fourth code value with the first code value; calculate a first expected value of the third code value; and perform the process when the third code value and the first expected value match.