Patents Examined by Roy Potter
  • Patent number: 10431622
    Abstract: The present technology relates to a solid-state imaging apparatus and an electronic apparatus that makes it possible to improve coloration and improve image quality. The solid-state imaging apparatus is formed so that, in a pixel array unit in which combinations of a first pixel corresponding to a color component of a plurality of color components and a second pixel having higher sensitivity to incident light as compared with the first pixel are two-dimensionally arrayed, a first electrical barrier formed between a first photoelectric conversion unit and a first unnecessary electric charge drain unit in the first pixel, and a second electrical barrier formed between a second photoelectric conversion unit and a second unnecessary electric charge drain unit in the second pixel have different heights, respectively. The present technology can be applied to, for example, a CMOS image sensor.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 1, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Kazuyoshi Yamashita
  • Patent number: 10424573
    Abstract: A packaging process of an electronic component is provided. By the packaging process of the disclosure, the electronic component is grinded by the back grinding process. Consequently, thickness of the electronic component may be reduced to less than or equal to 50 ?m. The packaging process may achieve ultra-thin thickness and reduce the space of the power module. Moreover, the packaging process forms the contact pads with drilling process and grinding process without photolithography process. Consequently, the packaging process is advantageous because of lower cost and uniform thickness of the contact pads.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: September 24, 2019
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventor: Beng Beng Lim
  • Patent number: 10403587
    Abstract: A radio frequency circuit includes, a multilayer substrate having a grounded base metal and a plurality of insulating layers and wiring layers formed over the grounded base metal and having a recess surrounded by the plurality of insulating layers and wiring layers over the grounded base metal, an upper substrate having a through-hole penetrating the upper substrate, a first semiconductor chip mounted on the upper surface of the upper substrate and electrically coupled to a metal film formed on the lower surface of the upper substrate, a metal pillar formed on the upper surface of the grounded base metal in the recess, and a solder buried in the through-hole and bonded to the metal film and the upper surface of the metal pillar. The metal film is bonded to a ground wiring layer electrically coupled to the grounded base metal among the plurality of wiring layers.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 3, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masaru Sato, Yukiyasu Furukawa
  • Patent number: 10381472
    Abstract: In a nitride-semiconductor field-effect transistor, an end on a recess side of a first insulating film is separated by a distance from an opening edge of the recess and an end on a recess side of a second insulating film is separated by a distance from the end on the recess side of the first insulating film. A part of a drain electrode out of the recess stretches toward a gate electrode side in an eaves shape, is formed over surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film from the recess, and contacts the surfaces of the nitride semiconductor laminate, the first insulating film, and the second insulating film.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Yutaka Nakayama, Junichiroh Koyama, Koichiro Fujita
  • Patent number: 10366856
    Abstract: Nanoscale field-emission devices are presented, wherein the devices include at least a pair of electrodes separated by a gap through which field emission of electrons from one electrode to the other occurs. The gap is dimensioned such that only a low voltage is required to induce field emission. As a result, the emitted electrons energy that is below the ionization potential of the gas or gasses that reside within the gap. In some embodiments, the gap is small enough that the distance between the electrodes is shorter than the mean-free path of electrons in air at atmospheric pressure. As a result, the field-emission devices do not require a vacuum environment for operation.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: July 30, 2019
    Assignee: CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Axel Scherer, William M. Jones, Danil M. Lukin, Sameer Walavalkar, Chieh-feng Chang
  • Patent number: 10367042
    Abstract: A display device includes an element substrate including a display area where a plurality of self-light-emitting elements are formed, and a driver IC disposed outside the display area in the element substrate. A first metal layer is disposed on the reverse side of the element substrate at a position opposite to the display area. A second metal layer is disposed with a space between the first metal layer and the second metal layer on the reverse side of the element substrate at a position opposite to the driver IC.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: July 30, 2019
    Assignee: Japan Display Inc.
    Inventors: Ryoichi Ito, Toshihiro Sato
  • Patent number: 10366881
    Abstract: A method for forming a heteroepitaxial layer includes forming an epitaxial grown layer on a monocrystalline substrate and patterning the epitaxial grown layer to form fins. The fins are converted to porous fins. A surface of the porous fins is treated to make the surface suitable for epitaxial growth. Lattice mismatch is compensated for between an epitaxially grown monocrystalline layer grown on the surface and the monocrystalline substrate by relaxing the epitaxially grown monocrystalline layer using the porous fins to form a relaxed heteroepitaxial interface with the monocrystalline substrate.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Keith E. Fogel, Jeehwan Kim, Devendra K. Sadana
  • Patent number: 10347854
    Abstract: The disclosure relates to a logic circuit. The logic circuit includes two ambipolar thin film transistors. Each of the two ambipolar thin film transistors includes a substrate; a semiconductor layer located on the substrate and including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are located on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer located on the substrate and covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The two ambipolar thin film transistors share the same substrate, the same gate, and the same drain.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 9, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10297521
    Abstract: A circuit substrate is provided with a base formed of ceramics. It includes a first face a second face; and a through hole penetrating from the first face to the second face; a through conductor: containing silver and copper as main components; disposed inside the through hole; and including a plurality of surfaces; and a metal layer in contact with at least one of the plurality of surfaces. The through conductor includes a eutectic region of silver and copper, disposed in a metal layer side of a diametrically center region of the through conductor; and a non-eutectic region of silver and copper, disposed in a central region of the diametrically center region of the through conductor.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 21, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Yuuichi Abe
  • Patent number: 10269879
    Abstract: A display device capable preventing or reducing luminance unevenness due to a voltage drop using an auxiliary electrode is provided. The display device may include a bank insulating layer that forms an under-cut region for connecting the auxiliary electrode to an upper electrode of a light-emitting structure. The bank insulating layer may include a first bank penetrating hole overlapping with the auxiliary electrode and a second bank penetrating hole spaced apart from the first bank penetrating hole. The second bank penetrating hole may overlap a lower penetrating hole of a lower passivation layer which is disposed between the auxiliary electrode and the bank insulating layer. The lower penetrating hole may overlap the auxiliary electrode.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 23, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sung-Bin Shim, Hye-Sook Kim
  • Patent number: 10262927
    Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazunori Hasegawa, Hiroi Oka
  • Patent number: 10249559
    Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
  • Patent number: 10236439
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a diameter that is different from a diameter of the free layer. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Manfred Ernst Schabes, Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10224456
    Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Patent number: 10217721
    Abstract: Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 26, 2019
    Assignee: Apple Inc.
    Inventors: James D. Kelly, William H. Radke, Steven J. Sfarzo
  • Patent number: 10141499
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a central axis that is offset from a central axis of the free layer. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted. The off-center design may be used to adjust the location of the stray-field injection in the free layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 27, 2018
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Manfred Ernst Schabes, Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10135024
    Abstract: A curved display device has a plurality of layers including elements for implementing an input image, and has a neutral plane (NP), a first area positioned in any one of upper and lower sides of the NP with compressive stress applied thereto, and a second area positioned in the other of the upper and lower sides of the NP with a tensile stress applied thereto The curved display device includes at least one first curved portion; and at least one second curved portion bent in a direction different from a direction of the first curved portion. The first curved portion and the second curved portion are different in thickness, and positions of the NPs.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 20, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Junjae Lee, Myeongah Shin
  • Patent number: 10128399
    Abstract: A lateral-effect position-sensing detector includes a second lateral-current collector layer, an electron barrier layer on the second lateral-current collector layer, an absorber layer on the electron barrier layer, a first lateral-current collector layer on the absorber layer, and a first elongate electrical contact and a second elongate electrical contact on each of the lateral-current collector layers. Incident light radiates a transparent first lateral-current collector layer to be absorbed by the undepleted absorber layer where electron and holes are generated. The depleted electron barrier layer prevents a flow of electrons from the absorber layer to the second lateral-current collector layer but allows electrons to flow to the second lateral-current collector layer. The lateral-effect position-sensing detector is sensitive to a lateral position between the first elongate electrical contact and the second elongate electrical contact of incident light on each of the lateral-current collector layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: HRL Laboratories, LLc
    Inventor: Daniel Yap
  • Patent number: 10083940
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 10084043
    Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy, Chandra S. Mohapatra, Sanaz K. Gardner, Marko Radosavljevic, Glenn A. Glass