Patents Examined by Roy Potter
  • Patent number: 10297521
    Abstract: A circuit substrate is provided with a base formed of ceramics. It includes a first face a second face; and a through hole penetrating from the first face to the second face; a through conductor: containing silver and copper as main components; disposed inside the through hole; and including a plurality of surfaces; and a metal layer in contact with at least one of the plurality of surfaces. The through conductor includes a eutectic region of silver and copper, disposed in a metal layer side of a diametrically center region of the through conductor; and a non-eutectic region of silver and copper, disposed in a central region of the diametrically center region of the through conductor.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 21, 2019
    Assignee: KYOCERA CORPORATION
    Inventor: Yuuichi Abe
  • Patent number: 10269879
    Abstract: A display device capable preventing or reducing luminance unevenness due to a voltage drop using an auxiliary electrode is provided. The display device may include a bank insulating layer that forms an under-cut region for connecting the auxiliary electrode to an upper electrode of a light-emitting structure. The bank insulating layer may include a first bank penetrating hole overlapping with the auxiliary electrode and a second bank penetrating hole spaced apart from the first bank penetrating hole. The second bank penetrating hole may overlap a lower penetrating hole of a lower passivation layer which is disposed between the auxiliary electrode and the bank insulating layer. The lower penetrating hole may overlap the auxiliary electrode.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: April 23, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Sung-Bin Shim, Hye-Sook Kim
  • Patent number: 10262927
    Abstract: Reliability of a semiconductor device is improved. For this, embodied is a basic idea that a semiconductor chip (CHP1) mounted on an Ag layer (AGL) is fixed by using a temporarily fixing material (TA) having tackiness without forming the temporarily fixing material (TA) on a surface of the Ag layer (AGL) having a porous structure as much as possible, is realized. More specifically, the temporarily fixing material (TA) is supplied so as to have a portion made in contact with a chip mounting part (TAB), and the semiconductor chip (CHP1) is also mounted on the Ag layer (AGL) so that one portion of a rear surface of the semiconductor chip (CHP1) is made in contact with the temporarily fixing material (TA).
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kazunori Hasegawa, Hiroi Oka
  • Patent number: 10249559
    Abstract: Ball grid assembly (BGA) bumping solder is formed on the back side of a laminate panel within a patterned temporary resist. Processes such as singulation and flip chip module assembly are conducted following BGA bumping with the temporary resist in place. The resist is removed from the back side of the singulated laminate panel prior to card assembly. Stand-off elements having relatively high melting points can be incorporated on the BGA side of the laminate panel to ensure a minimum assembly solder collapse height. Alignment assemblies are formed on the socket-facing side of an LGA module using elements having relatively high melting points and injected solder.
    Type: Grant
    Filed: January 18, 2016
    Date of Patent: April 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jae-Woong Nah, Charles L. Reynolds, Katsuyuki Sakuma
  • Patent number: 10236439
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a diameter that is different from a diameter of the free layer. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: March 19, 2019
    Assignee: Spin Memory, Inc.
    Inventors: Manfred Ernst Schabes, Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10224456
    Abstract: A method of fabricating a light emitting diode, which includes an n-type contact layer and a light generating structure adjacent to the n-type contact layer, is provided. The light generating structure includes a set of quantum wells. The contact layer and light generating structure can be configured so that a difference between an energy of the n-type contact layer and an electron ground state energy of a quantum well is greater than an energy of a polar optical phonon in a material of the light generating structure. Additionally, the light generating structure can be configured so that its width is comparable to a mean free path for emission of a polar optical phonon by an electron injected into the light generating structure.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Patent number: 10217721
    Abstract: Memory packages, memory modules, and circuit boards are described. In an embodiment, single channel memory packages are mounted on opposite sides of a circuit board designed with a first side also designed to accept dual channel memory packages. Alternatively, dual channel memory packages may be mounted on a first side of a circuit board that is also designed to accept single channel packages on opposite sides.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: February 26, 2019
    Assignee: Apple Inc.
    Inventors: James D. Kelly, William H. Radke, Steven J. Sfarzo
  • Patent number: 10141499
    Abstract: A magnetoresistive random-access memory (MRAM) is disclosed. The MRAM device includes a perpendicular magnetic tunnel junction device having a reference layer, a free layer, and a precessional spin current magnetic layer. The precessional spin current magnetic layer has a central axis that is offset from a central axis of the free layer. The device is designed to provide control over the injection of stray fields and the electronic coupling between the precessional spin current magnetic layer and the free layer. Switching speed, switching current, and thermal barrier height for the device can be adjusted. The off-center design may be used to adjust the location of the stray-field injection in the free layer.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: November 27, 2018
    Assignee: Spin Transfer Technologies, Inc.
    Inventors: Manfred Ernst Schabes, Mustafa Michael Pinarbasi, Bartlomiej Adam Kardasz
  • Patent number: 10135024
    Abstract: A curved display device has a plurality of layers including elements for implementing an input image, and has a neutral plane (NP), a first area positioned in any one of upper and lower sides of the NP with compressive stress applied thereto, and a second area positioned in the other of the upper and lower sides of the NP with a tensile stress applied thereto The curved display device includes at least one first curved portion; and at least one second curved portion bent in a direction different from a direction of the first curved portion. The first curved portion and the second curved portion are different in thickness, and positions of the NPs.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: November 20, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Junjae Lee, Myeongah Shin
  • Patent number: 10128399
    Abstract: A lateral-effect position-sensing detector includes a second lateral-current collector layer, an electron barrier layer on the second lateral-current collector layer, an absorber layer on the electron barrier layer, a first lateral-current collector layer on the absorber layer, and a first elongate electrical contact and a second elongate electrical contact on each of the lateral-current collector layers. Incident light radiates a transparent first lateral-current collector layer to be absorbed by the undepleted absorber layer where electron and holes are generated. The depleted electron barrier layer prevents a flow of electrons from the absorber layer to the second lateral-current collector layer but allows electrons to flow to the second lateral-current collector layer. The lateral-effect position-sensing detector is sensitive to a lateral position between the first elongate electrical contact and the second elongate electrical contact of incident light on each of the lateral-current collector layer.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: November 13, 2018
    Assignee: HRL Laboratories, LLc
    Inventor: Daniel Yap
  • Patent number: 10083940
    Abstract: Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the substrate. A second die is coupled beneath the lower surface of the substrate and is disposed over the first die. A thermal contact pad is arranged beneath a lower surface of the second die and an upper surface of the first die. The thermal contact pad thermally isolates the first die from the second die.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh
  • Patent number: 10084043
    Abstract: An integrated circuit die includes a quad-gate device nanowire of channel material for a transistor (e.g., single material or stack to be a channel of a MOS device) formed by removing a portion of a sub-fin material from below the channel material, where the sub-fin material was grown in an aspect ration trapping (ART) trench. In some cases, in the formation of such nanowires, it is possible to remove the defective fin material or area under the channel. Such removal isolates the fin channel, removes the fin defects and leakage paths, and forms the nanowire of channel material having four exposed surfaces upon which gate material may be formed.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: September 25, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros, Willy Rachmady, Tahir Ghani, Anand S. Murthy, Chandra S. Mohapatra, Sanaz K. Gardner, Marko Radosavljevic, Glenn A. Glass
  • Patent number: 10083855
    Abstract: A method of preparing a single crystal semiconductor handle wafer in the manufacture of a silicon-on-insulator device is provided. The method comprises forming a multilayer of passivated semiconductors layers on a dielectric layer of a high resistivity single crystal semiconductor handle wafer. The method additionally comprises forming a semiconductor oxide layer on the multilayer of passivated semiconductor layers. The multilayer of passivated semiconductor layers comprise materials suitable for use as charge trapping layers between a high resistivity substrate and a buried oxide layer in a semiconductor on insulator structure.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: September 25, 2018
    Assignee: GlobalWafers Co., Ltd.
    Inventors: Igor Peidous, Illaria Katia Marianna Pellicano
  • Patent number: 10079359
    Abstract: An organic light emitting diode according to the present disclosure includes a first electrode, a second electrode overlapping the first electrode, and an emission layer disposed between the first electrode and the second electrode. The second electrode includes a bottom region and a top region. The bottom region includes a MgAg alloy including more Mg than Ag. The top region includes a AgMg alloy including more Ag than Mg.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: September 18, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Eun Ho Kim, Da Hye Kim, Su Hwan Lee, Sang Yeol Kim
  • Patent number: 10079204
    Abstract: A light-erasable embedded memory device and a method for manufacturing the same are provided in the present invention. The light-erasable embedded memory device includes a substrate with a memory region and a core circuit region, a floating gate on the memory region of the substrate, at least two light-absorbing films above the floating gate, wherein each light-absorbing film is provided with at least one dummy via hole overlapping the floating gate, and a dielectric layer on each light-absorbing film and filling up the dummy via holes.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: September 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Hao Su, Chow Yee Lim, Chao Jiang, Hong Liao
  • Patent number: 10068926
    Abstract: A semiconductor device includes a pixel electrode and a transistor which includes a first gate electrode, a first insulating layer over the first gate electrode, a semiconductor layer over the first insulating layer, a second insulating layer over the semiconductor layer, and a second gate electrode. The pixel electrode and the second gate electrode are provided over the second insulating layer. The first gate electrode has a region overlapping with the semiconductor layer with the first insulating layer provided therebetween. The second gate electrode has a region overlapping with the semiconductor layer with the second insulating layer provided therebetween. A first region is at least part of a region where the second gate electrode overlaps with the semiconductor layer. A second region is at least part of a region where the pixel electrode is provided. The second insulating layer is thinner in the first region than in the second region.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: September 4, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 10062815
    Abstract: A light emitting device includes a carrier, a light emitting chip, and a covering part disposed on the carrier. The carrier includes a board, a guiding metal layer, and a sealing material. The board has a first surface, a second surface, and a through vent that is divided into a first partial hole and a second partial hole. The first partial hole extends from the first surface to the second partial hole, and the second partial hole extends from the second surface to the first partial hole. The guiding metal layer is formed on the second surface and in the second partial hole, and covers the sidewall of the second partial hole. The guiding metal layer extends from the second partial hole to the second surface, and does not cover the sidewall of the first partial hole and the first surface. The sealing material seals the second partial hole.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 28, 2018
    Assignee: UNISTARS CORPORATION
    Inventors: Hsin-Hsien Hsieh, Shang-Yi Wu
  • Patent number: 10056478
    Abstract: Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: August 21, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Wei Tsai, King-Yuen Wong, Chih-Wen Hsiung, Ming-Cheng Lin
  • Patent number: 10032831
    Abstract: A display device preventing light leak to an adjacent pixel and thus to prevent color mixing to improve image quality is provided. An organic EL display device includes a plurality of pixels. The plurality of pixels each include a light emitting element; the light emitting element includes a pixel electrode, a common electrode, an EL common layer, and a light emitting layer; the EL common layer and the light emitting layer are provided between the pixel electrode and the common electrode; the EL common layer covers a main surface and an end of the pixel electrode; the pixel electrode is provided on an insulating layer; and the common electrode is in contact with the insulating layer between the plurality of pixels.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 24, 2018
    Assignee: JAPAN DISPLAY INC.
    Inventors: Yuko Matsumoto, Toshihiro Sato
  • Patent number: 10032918
    Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: July 24, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Ryo Tokumaru, Yasumasa Yamane, Kiyofumi Ogino, Taichi Endo, Hajime Kimura