Patents Examined by Russell M. Kobert
  • Patent number: 7230414
    Abstract: A current sensor that includes a pair of segments. Each of the segments includes magnetically permeable cores that can be joined together. A winding is used to substantially encircle one of the cores.
    Type: Grant
    Filed: December 29, 2004
    Date of Patent: June 12, 2007
    Assignee: Veris Industries, LLC
    Inventor: David A. Bruno
  • Patent number: 7187187
    Abstract: A signal acquisition probing system uses a micro-cavity laser to acquire an electrical signal from a device under test. The micro-cavity laser has a VCSEL gain medium and an electro-optic optical resonant cavity. The micro-cavity laser is pumped by an external laser source and generates a frequency modulated optical signal derived from the device under test electrical signal creating an electro-magnetic field distribution in electro-optic material in the micro-cavity laser that overlaps the optical path of the optical signal propagating in the electro-optic material. The frequency modulated optical signal is coupled to an optical receiver which converts the frequency modulated optical signal to an electrical signal. The electrical signal is coupled to measurement test instrument for processing and displaying of the electrical signal.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: March 6, 2007
    Assignee: Tektronix, Inc.
    Inventors: Christopher P. Yakymyshyn, William Q. Law, William A. Hagerup
  • Patent number: 7123041
    Abstract: The present invention provides an LSI inspection method and a defect inspection data analysis apparatus capable of shortening a time needed for a wafer test. In a first database 11 is stored inspection data obtained when each defect inspection apparatus 20 inspects a wafer for defects in the front-end process. In a second database 12 are stored non-conforming article judgment criteria for each predetermined type of defect, according to which a non-conforming chip is judged. A defective chip identifying portion 16 identifies a chip having a defect and identifies the type of defect for each defect that the identified chip has, on the basis of the inspection data. For each identified chip, a non-conforming chip judging portion 17 judges whether the chip is a non-conforming article or not according to the non-conforming article judgment criteria corresponding to the type of defect for each defect, and obtains position information within the wafer surface of a chip judged as being a non-conforming article.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: October 17, 2006
    Assignee: UMC Japan
    Inventor: Yoji Hata
  • Patent number: 7123037
    Abstract: An integrated circuit (IC) temperature sensing device includes a temperature sensor positioned within a conductive temperature sensor housing and a thermal insulator surrounding the conductive temperature sensor housing. The sensor housing and thermal insulator are positioned within an IC temperature control block that heats or cools the IC. The temperature sensor housing comes into thermal contact with an IC undergoing burning-in, testing or programming. The temperature sensor housing provides a short thermal path between the IC under test and the temperature sensor. The thermal insulator thermally isolates the temperature sensor from the temperature control block so that the temperature sensor predominantly measures the temperature of the IC.
    Type: Grant
    Filed: August 17, 2004
    Date of Patent: October 17, 2006
    Assignee: WELLS-CTI, LLC
    Inventor: Christopher A. Lopez
  • Patent number: 7109739
    Abstract: A wafer-level testing arrangement for opto-electronic devices formed in a silicon-on-insulator (SOI) wafer structure utilizes a single opto-electronic testing element to perform both optical and electrical testing. Beam steering optics may be formed on the testing element and used to facilitate the coupling between optical probe signals and optical coupling elements (e.g., prism couplers, gratings) formed on the top surface of the SOI structure. The optical test signals are thereafter directed into optical waveguides formed in the top layer of the SOI structure. The opto-electronic testing element also comprises a plurality of electrical test pins that are positioned to contact a plurality of bondpad test sites on the opto-electronic device and perform electrical testing operations. The optical test signal results may be converted into electrical representations within the SOI structure and thus returned to the testing element as electrical signals.
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: September 19, 2006
    Assignee: SiOptical, Inc.
    Inventors: Prakash Gothoskar, Margaret Ghiron, Robert Keith Montgomery, Vipulkumar Patel, Kalpendu Shastri, Soham Pathak, David Piede, Katherine A. Yanushefski
  • Patent number: 7105364
    Abstract: Semiconductor dice are electrically tested prior to final assembly. Dice failing the test are identified and not packaged. However, “good dice” (i.e., those dice that passed testing) in proximity to the failed dice frequently fail prematurely in the field. Therefore, in one embodiment, a method to identify those dice having a probability for early failure includes identifying a core die and a die cluster, adding the core die and at least one additional die from the die cluster to a weighted character map, and assigning a weighting value to each of the dice added to the weighted character map. At least one tier of buffer dice is then added to the weighted character map adjacent to each die on the weighted character map. Both the dice from the die cluster and the tier of buffer dice are marked, thereby preventing those dice from being packaged and consequently, shipped to customers.
    Type: Grant
    Filed: September 14, 2004
    Date of Patent: September 12, 2006
    Assignee: Atmel Corporation
    Inventors: Paul I. Suciu, Kristopher R. Marcus, Charles B. Friedberg
  • Patent number: 7105366
    Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.
    Type: Grant
    Filed: September 8, 2005
    Date of Patent: September 12, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Chad A. Cobbley, John VanNortwick, Bret K. Street, Tongbi Jiang
  • Patent number: 7102370
    Abstract: A micro-browser has pair of rods each rod entering a corresponding bore in a sleeve that retains them, and that may itself be carried by a grip shaped to be rotated between a thumb and a finger. The edge of a small circuit board is soldered at the distal end of the rod. One of the rods is allowed to rotate within its bore in the sleeve, while the other is held stationary by a notch in the sleeve. The rotatable rod has a captive spring that resists the force of probe contact. Each board carries a coupling network connected to a short sharp probe tip bent downward away from the plane of its board, allowing the distance between the probe tips to be a function of the amount of rotation. The other end of each coupling network is coupled to a short length of a respective 50 ? coaxial cable that passes through an axial slot in the grip to enter an amplifier pod that drives a main cable leading to test equipment. The rods may be held within the bores by friction created by slight bends in the rods.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: September 5, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: James E. Cannon, David J. Dascher, Michael T. McTigue, Stuart O. Hall
  • Patent number: 7098681
    Abstract: A semiconductor device has a boosting circuit configured to generate a boosting potential to an output line. An internal circuit is supplied with the boosting potential from the boosting circuit via the output line. A test line is connected to the output line. A control circuit is arranged between the output line and the test line and configured to shut off a current flowing into the test line from the output line during a boosting operation of the boosting circuit.
    Type: Grant
    Filed: July 23, 2004
    Date of Patent: August 29, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Junichiro Noda
  • Patent number: 7088117
    Abstract: A cartridge (10) includes a chuck plate (12) for receiving a wafer (74) and a probe plate (14) for establishing electrical contact with the wafer. In use, a mechanical connecting device (90) locks the chuck plate and the probe plate fixed relative to one another to maintain alignment of the wafer and the probe plate. Preferably, electrical contact with the wafer is established using a probe card (50) that is movably mounted to the probe plate by means of a plurality of leaf springs (52.) The mechanical connecting device is preferably a kinematic coupling including a male connector (94) and first and second opposed jaws (122, 124.) Each of the jaws is pivotable from a retracted position in which the male connector can be inserted between the jaws and an engaging position in which the jaws prevent withdrawal of the male connector from between the jaws. The male connector is movable between an extended and a retracted position, and is biased towards the retracted position.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: August 8, 2006
    Assignee: Aehr Test System
    Inventors: Frank Otto Uher, John William Andberg, Mark Charles Carbone, Donald Paul Richmond, II
  • Patent number: 7088120
    Abstract: A probe device including a cantilever. A probe is attached to the cantilever and is allocated to be opposed to a surface of a sample attached thereto. An apparatus is provided with the probe device, which is capable of carrying out measurement of the sample while switching at a predetermined period two operating modes, a tapping mode for measuring a surface structure of the sample while vibrating the cantilever and a point contact mode for measuring an electrical characteristic of the sample while bringing the probe into contact with the sample.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: August 8, 2006
    Assignee: Osaka University
    Inventors: Takuya Matsumoto, Yoicho Otsuka, Yasuhisa Naitoh, Tomoji Kawai
  • Patent number: 7078890
    Abstract: A clamping assembly for connecting a first plurality of contacts to a second plurality of contacts on a circuit board. The circuit board has a first outer face and a second outer face. The second contacts are arranged on at least one of the first and second outer faces. The clamping assembly includes a first assembly having a first inner face, and a second assembly having a second inner face substantially parallel to the first inner face. The first plurality of contacts are arranged on at least one of the first and second inner faces. Mechanical alignment features facilitate alignment of the first contacts with the second contacts. The first and second assemblies are configured to enable relative motion therebetween to effect clamping of the first and second inner faces to the first and second outer faces of the circuit board.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: July 18, 2006
    Assignee: Xandex, Inc.
    Inventors: Roger Sinsheimer, D. Evan Williams
  • Patent number: 7075322
    Abstract: A testing apparatus (2) includes a probe station (21), a micropositioner (22), a probe (23), an electronic camera (27), and a monitor. The probe station has a working surface (211) for supporting an object to be tested. The micropositioner is located on the working surface. The probe is mounted on the micropositioner, and is used for testing circuits of the object. The electronic camera is mounted on the micropositioner, and is used for taking images of the probe and the circuits. The monitor connects with the electronic camera, and is used for displaying the images. Because the testing apparatus utilizes the electronic camera to take images of the probes and the circuits, and the images are displayed on the monitor, a user can conveniently observe the testing process. Further, the electronic cameras help reduce the overall cost of the testing apparatus.
    Type: Grant
    Filed: May 16, 2005
    Date of Patent: July 11, 2006
    Assignee: Innolux Display Corp.
    Inventor: Mao-Yuan Huang
  • Patent number: 7075318
    Abstract: Methods for determining an electrical parameter of an insulating film are provided. One method includes measuring a surface potential of a leaky insulating film without inducing leakage across the insulating film and determining the electrical parameter from the surface potential. Another method includes applying an electrical field across the insulating film. Leakage across the insulating film caused by the electrical field is negligible. The method also includes measuring a surface potential of the specimen and determining a potential of the substrate. In addition, the method includes determining a pure voltage across the insulating film from the surface potential and the substrate potential. The method further includes determining the electrical parameter from the pure voltage. The electrical parameter may be capacitance or electrical thickness of the insulating film.
    Type: Grant
    Filed: January 9, 2004
    Date of Patent: July 11, 2006
    Assignee: KLA-Tencor Technologies Corp.
    Inventors: Xiafang (Michelle) Zhang, Zhiwei (Steve) Xu, Jianou Shi, Bao Vu, Thomas G. Miller, Gregory S. Horner
  • Patent number: 7061250
    Abstract: Disclosed is a novel method and apparatus for acquiring multiple capacitively sensed measurements from a circuit under test. Multiple digital sources are respectively connected to stimulate multiple respective first ends of multiple respective nets of interest. Respective second ends of the multiple respective nets of interest are capacitively sensed. The respective capacitively coupled signals are digitally sampled and shift correlated with respective expected digital signatures. If a high level of correlation is found for a given net, the net is electrically intact; otherwise, the net is characterized by either an open or some other fault that prevents it from meeting specification.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: June 13, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Curtis A. Tesdahl, Ronald J. Peiffer
  • Patent number: 7042240
    Abstract: An integrated circuit (IC) package testing apparatus integrates a temperature sensor, heater (or cooler), and controller within a single modular unit. The controller is a microprocessor embedded within the modular unit and in communication with the sensor and heater. The controller allows a selected testing temperature to be input by a user via a communications link to the controller. Each IC package has its testing temperature individually controlled by a controller. The module is easily attached and removed from an open-top socket through the use of latches on the testing socket. Many IC packages can be quickly placed and removed from testing sockets when a matrix of sensors and heaters (or coolers) are located on a single top attach plate with the sensors and heaters (or coolers) individually spring-loaded on the single top attach plate.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: May 9, 2006
    Assignee: Wells-CTI, LLC
    Inventors: Christopher A. Lopez, Brian J. Denheyer, Gordon B. Kuenster
  • Patent number: 7038442
    Abstract: A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the analysis may further involve obtaining a likelihood that the correlated photons were emitted by a transistor. After correlation, the analysis may also further involve assigning a weight to individual photon emissions as a function of the correlation. The weight, in some instances, reflecting a likelihood that the photons were emitted by a transistor. The analysis may further involve automatically identifying transistors in a photon emission image.
    Type: Grant
    Filed: January 20, 2005
    Date of Patent: May 2, 2006
    Assignee: Credence Systems Corporation
    Inventors: Romain Desplats, Patricia Le Coupanec, William K. Lo, Philippe Perdu, Steven Kasapi
  • Patent number: 7038484
    Abstract: A display device includes a first inspection wiring line that is connected to first wiring lines of a first wiring line group and to third wiring lines of a second wiring line group, and a second inspection wiring line that is connected to second wiring lines of the first wiring line group, which neighbor the first wiring lines, and to fourth wiring lines of the second wiring line group, which neighbor the third wiring lines.
    Type: Grant
    Filed: August 3, 2005
    Date of Patent: May 2, 2006
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Kazuyuki Harada, Yohei Kimura, Koji Nakayama
  • Patent number: 7038478
    Abstract: A large array probe/contact having spring characteristics for relieving stress in the contact caused, for example, by temperature change is fabricated using a unique combination of semiconductor fabrication operations. The contacts in the array have a “U” shaped resilient portion, are fixed at one end to a substrate and have an accessible low electrical noise contact tip. The contacts are encapsulated on the substrate in an elastomer to provide additional stress relief resilience, support and protection from damage during handling.
    Type: Grant
    Filed: November 23, 2004
    Date of Patent: May 2, 2006
    Inventor: Donald M. Macintyre
  • Patent number: 7034520
    Abstract: A product change tool for selectively engaging a product change element with an IC tester interface and disengaging the product change element from the tester interface includes a mobile frame mounted to a base frame and constrained to move relative to the base frame along an axis of linear movement, and a force mechanism for urging the mobile frame to move along the axis of linear movement relative to the base frame. The force mechanism includes first and second links pivotally connected together at their proximal ends and secured at their distal ends to the mobile frame and the base frame respectively. The distal ends of the links are spaced apart along the axis of linear movement and the proximal ends of the links are between the distal ends relative to that axis.
    Type: Grant
    Filed: September 9, 2005
    Date of Patent: April 25, 2006
    Assignee: Credence Systems Corporation
    Inventors: Wayne H. Miller, Chris S. Paretich, James K. Lubin, Stuart M. Firestone