Abstract: A semiconductor testing device is used for testing a semiconductor device which has at least one spherical connection terminal. The testing device includes an insulating substrate having an opening formed there in at a position corresponding to the position of the spherical connection terminal, and a contact member, formed on the insulating substrate, including a connection portion which is connected with the spherical connection terminal, at least the connection portion being deformable and extending into the opening.

Abstract: A printed circuit board test fixture that includes a mounting plate which supports a printed circuit board to be tested is provided. A probe support plate holder, positioned above the mounting plate, mechanically couples to a probe support plate and holds the probe support plate opposite the mounting plate. A base plate is positioned below the mounting plate. At least three alignment sliders are included, with each alignment slider including a guide rail and a runner block slidably coupled to the guide rail. The guide rails are coupled to the base plate. The runner blocks are coupled to the mounting plate to thereby allow for movement of the mounting plate only along an axis perpendicular to a plane of the mounting plate. Multiple balancing sliders coupled to the base plate and positioned at a back end of the printed circuit board test fixture.

Abstract: A near electric-field probe is driven by a short laser pulse delayed through an optical delay-line for detecting vectors of near-field components of electrical signals propagating through a device under test including an electrical device or an electronic circuit based on a sampling principle. The near-field probe includes a photoconductive switch assembly including a thin semiconductor photoconductive body, at least two separated switch electrodes formed on the thin semiconductor photoconductive body, and an electrode gap formed between the two separated switch electrodes; and an optical waveguide attached to one side of the photoconductive switch assembly by using an optical adhesive, wherein the optical waveguide is partially coated with conductive material on the outer surface thereof.

Abstract: A method for testing integrated circuits, including measuring a current signature delta value of a device under test and comparing the current signature delta value to a threshold current signature delta value to determine whether the current signature delta value is greater than the threshold current signature delta value. If the current signature delta value exceeds the threshold current signature delta value, the integrated circuit is rejected. Integrated circuits are also rejected if the post-stress current signature value exceeds a maximum current signature value, even though the current signature delta value is less than the threshold current signature delta value. In addition, an apparatus for testing integrated circuits is disclosed.

Abstract: The invention concerns a method for making a card with tips for testing semiconductor chips with microsphere bond pads. A first adhesive coat is vacuum deposited on a flexible polyimide film, followed by a second metal coat. A combination of UV photolithography and electroforming of a metal material enables to obtain the implantation of the tips. The pattern of the strip conductors is obtained by a second UV lithography operation whereby the second metal layer and the first adhesive coat are etched. An insulating protective resist is deposited on the active conductive zone. The flexible film is mounted on a truncated maintaining component whereof the vertical translational and planar rotational movements are made possible by a guide supported on a spring suspension. The defective alignment between the plane of the tips and the plane of the tips and the printed circuit plane is corrected by a correcting system with three support points adjustable with screws.

Abstract: Method and system for periodically measuring the junction temperature of a semiconductor device. The junction exited by at least two sequential predetermined currents of different magnitudes the voltage response of the junction to the at least two currents is measured and the temperature of the junction is calculated, while substantially canceling ohmic effects, by using the voltage response and a correction factor obtained by periodically. Whenever desired, the junction is exited by a set of at least four sequential different currents having known ratios. The voltage response to the set is measured and the correction factor is calculated by using each voltage response to the set.

Abstract: A test socket including a contactor having a distal end which is received within a tapered retainer for guiding the distal end of the contactor and into a terminal housing having a counterbore such that movement of the distal end of the contactor is restricted by the counterbore of the terminal is disclosed.

Abstract: An apparatus and method for positioning an integrated circuit (IC) for test in a test assembly. An IC positioning mechanism is provided that permits ready resetting of the position of the device that mounts an IC onto a test socket, thereby permitting efficient modification of a test assembly to accept different sized ICs. A mechanism for preventing inadvertent opening of the test assembly is also disclosed.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A metallic leadframe for use with a semiconductor chip intended for operation in a changing magnetic field comprises a chip mount pad having at least one slit penetrating the whole thickness of the pad and substantially traversing the area of the pad from one edge to the opposite edge. This slit is wide enough to interrupt electron flow in the pad plane, but not wide enough to significantly reduce thermal conduction in a direction normal to the pad plane, whereby the slit is operable to disrupt eddy currents induced in the pad by the changing magnetic field.

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a support member over the recess configured to electrically engage a bumped contact. The support member is suspended over the recess on spiral leads formed on a surface of the substrate. The spiral leads allow the support member to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the spiral leads twist the support member relative to the bumped contact to facilitate penetration of oxide layers thereon. The spiral leads can be formed by attaching a polymer substrate with the leads thereon to the substrate, or by forming a patterned metal layer on the substrate. In an alternate embodiment contact, the support member is suspended over the surface of the substrate on raised spring segment leads.

Abstract: The invention provides a contactor assembly.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A device for docking two means (100, 200), more particularly a probe (100) and a tester (200), including a first mounting board (110) arranged at the first means (100) and a second mounting board (210) arranged at the second means (200) which in the docked condition of the means (100, 200) are adjoined in a docking plane, the first mounting board (110) being provided with a recess (111) oriented inclined to the docking plane for engaging at least one peg (220) shiftingly mounted on the second mounting board (210), the second mounting board (210) comprising an actuator (300) by means of which the peg (220) guided in the recess (111) is shiftable between an open position and a docked position mutually clamping the first mounting board (110) and the second mounting board (210), wherein the actuator (300) has a slide (310, 311) mounting the peg (220) which is movable by means of a spindle (330, 331) between the open position and the docked position of the peg (220) in order to achieve a compact design and relativ

Abstract: A digital eddy current proximity system including a digital impedance measuring device for digitally measuring the proximity probes impedance correlative to displacement motion and position of a metallic target object being monitored. The system further including a cable-length calibration method, an automatic material identification and calibration method, a material insensitive method, an inductive ratio method and advanced sensing characteristics.

Abstract: A mechanical apparatus for testing a plethora of RF devices using test resources that are quickly and easily replaced is disclosed. The mechanical apparatus is located within an RF enclosure, and contains space for one or more test resources, or customizations, to be installed and applied to a device under test (DUT). The mechanical apparatus is coupled to the RF enclosure through a nest plate coupling to a drawer plate. This coupling is made into a tight seal through the use of o-ring elements that enables pneumatic pressure to be made available within the mechanical apparatus. The mechanical apparatus has a stationary base assembly, a lower nest assembly and an upper nest assembly. The DUT may be placed between the upper nest assembly and lower nest assembly, where the upper nest assembly and lower nest assembly may be coupled to test resources that may be applied to the DUT.

Abstract: A single gas tight system may perform multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a full-substrate probing device. A temperature control device is used to heat the wafer during an oxide reduction process or during burn-in of the wafer. During the oxide reduction process, hydrogen is introduced into the chamber, and the wafer is heated so that the oxides on the contact pads can combine with hydrogen to form water vapor, thus reducing the thickness of the oxides. A computer analyzes the test and/or burn-in data and provides control signals for repairing or programming the integrated circuits.

Abstract: A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.