Abstract: An integrated circuit (IC) package testing device using a selectable number of leaf springs to provide a resilient and consistent normal force to the IC package and the method of operating the device. The leaf springs are shaped to provide the proper compliance and resilient force and are shaped to fit side-by-side within the lid of the device. The springs can be easily changed for differently sized IC packages.

Abstract: In an apparatus and method for determining a permittivity of a dielectric layer on a semiconductor wafer, a thickness of the dielectric layer is determined and a topside of the wafer is moved into contact with a spherical portion of an at least partially spherical and electrically conductive surface. An electrical stimulus is applied between the electrically conductive surface and the semiconducting material. A capacitance of a capacitor comprised of the electrically conductive surface, the semiconductor material and the dielectric layer is determined from the applied stimulus. A permittivity of the dielectric layer is then determined as a function of the capacitance and the thickness of the dielectric layer.

Abstract: An exemplary engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate is described. Constructions are disclosed for testing apparatus comprising an engagement probe having an outer surface comprising a grouping of a plurality of electrically conductive projecting apexes positioned in proximity to one another to engage a single test pad on a semiconductor substrate.

Abstract: There is disclosed apparatus for socketing and testing integrated circuits, particularly RF and high-frequency integrated circuits in high density and fine pitch packages, and methods of operating the same. An exemplary apparatus includes an air machine and a housing. The housing includes a universal printed circuit board that is operable to receive a device under test, a controller that is operable to control testing of the received device under test, and a power supply. The housing and the air machine are associable to form an at least substantially air-tight chamber ensconcing the received device under test.

Abstract: A semiconductor chip is provided with a phase comparison circuit (1), in addition to an integrated circuit implementing a normal operation. The phase comparison circuit (1) compares phases between an internal signal (A) of the integrated circuit and an external signal and outputs a monitor signal (MONSIG) expressing the result of this comparison outward from the semiconductor chip. Thus, the phase of the internal signal (A) of the integrated circuit can be directly detected.

Abstract: The present invention utilizes wafer acceptance testing equipment to fast monitor the quality of an insulation layer. A plurality of swing time-dependent DC ramping voltages are applied to one of the electrode plates in a capacitor and each corresponding leakage current is measured to calculate each corresponding ? value. Then, a ratio of each ? value is calculated and a ?-voltage curve is plotted to actually simulate the device failure.

Abstract: A system for monitoring internal states of an integrated circuit includes logic nodes, selection logic and a monitor unit. The logic nodes are disposed within the integrated circuit and the selection logic is coupled to monitor pins externally accessible on the integrated circuit. The selection logic retrieves internal states of select logic nodes based on signals applied via the monitor pins. The monitor unit reads the internal states of the select logic nodes via the monitor pins.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract: Disclosed is a novel method and apparatus for acquiring multiple capacitively sensed measurements from a circuit under test. Multiple digital sources are respectively connected to stimulate multiple respective first ends of multiple respective nets of interest. Respective second ends of the multiple respective nets of interest are capacitively sensed. The respective capacitively coupled signals are digitally sampled and shift correlated with respective expected digital signatures. If a high level of correlation is found for a given net, the net is electrically intact; otherwise, the net is characterized by either an open or some other fault that prevents it from meeting specification.

Abstract: A power detector for measuring the power transfer between a circuit for emitting an electrical signal and a first conductor that receives the emitted electrical signal. The emitted signal causes a magnetic field to be generated in the first conductor. A coupling detection circuit measures an electric current that arises in a second conductor that is proximate and electrically coupled to the first conductor. The measured electric current in the second conductor is used to determine the power transfer between the emitting circuit and the first conductor. The first and second conductors can be bond wires within an integrated circuit package, and the coupling detection circuit can be disposed in a semiconductor substrate within the integrated circuit package.

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a support member over the recess configured to electrically engage a bumped contact. The support member is suspended over the recess on spiral leads formed on a surface of the substrate. The spiral leads allow the support member to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the spiral leads twist the support member relative to the bumped contact to facilitate penetration of oxide layers thereon. The spiral leads can be formed by attaching a polymer substrate with the leads thereon to the substrate, or by forming a patterned metal layer on the substrate. In an alternate embodiment contact, the support member is suspended over the surface of the substrate on raised spring segment leads.

Abstract: A circuit and a method determine at least one electrical characteristic variable for an integrated circuit. Two or more successively produced states of a reference signal are recorded and counted in a first recording unit to produce an output voltage in a voltage generator circuit for the integrated circuit, and the number of detected states is stored. Furthermore, a time duration within which the states of the reference signal are recorded is recorded in a second recording unit. The numerical values are output via an output circuit for determining the electrical characteristic variable. At least one electrical characteristic variable such as a voltage, current and/or power value for the integrated circuit, is calculated from the number of successively recorded states of the reference signal and from the time duration. It is therefore possible to obtain accurate values relating to the operation of the integrated circuit with comparatively little complexity.

Abstract: A method and a probe structure are provided for implementing multiple signals probing of a printed circuit board. A probe structure is formed on an outside surface of the printed circuit board. A resistor is electrically connected with an associated via with a signal to be monitored. A path to a predefined probe location for monitoring the signal is defined from the resistor using the probe structure.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract: A method of analysis of a time interval between two selected measurement edges of interest includes locking a plurality of at least three substantially interchangeable oscillators to a common reference frequency, the oscillators containing digital locked-loop (DLL) circuit architecture. The method includes operating one oscillator as a timebase oscillator, and operating the other oscillators as edge-resettable measurement oscillators. The method further includes coupling one oscillator with a switched and physically-immutable parametric variation, producing an offset in the frequency of the coupled oscillator relative to the frequency of the other oscillators.

Abstract: A method and apparatus for laser-assisted fault mapping which synchronizes the laser control with the tester unit. The inventive method provides for laser-assisted pseudo-static fault mapping to localize defects in a device whose inputs are being stimulated dynamically by a tester. It further provides for laser-assisted dynamic soft error mapping, to localize in terms of location and to correlate with respect to a specific test vector, sensitive areas in a device by utilizing device performance criteria such as pass-fail status outputs. The apparatus includes a fully controllable dynamic laser stimulation apparatus connected to a control unit that provides complete synchronization with a tester unit.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A method of testing an integrated circuit includes applying a voltage to one of the pins of the integrated circuit. The pin is floated for a predetermined time. A measurement is performed after the predetermined time. The measurement involves sampling the RC time constant of leakage current of the pins.