Abstract: Provided is an operating method of a storage device including a memory controller and a memory device, the operating method including storing a plurality of streams received from a host in the memory device; performing a management operation on a first storage region of the memory device in which a first stream from among the plurality of streams is stored; and performing a management operation on a second storage region of the memory device in which a second stream selected from among the plurality of streams based on an attribute of the first stream is stored.

Abstract: A distributed storage space management method, a computing device and a storage medium are provided. An embodiment is applied to a hardware smart card, which is deployed on a local host as a local hardware smart card. A corresponding storage space is partitioned for a local virtual device from a pre-configured storage device; the partitioned storage space is simulated to generate a simulated storage device corresponding to the local virtual device, for use by the local virtual device. A storage space application request of a remote hardware smart card is received, and according to the request, a corresponding storage space is partitioned for a remote virtual device from the pre-configured storage device, so that the partitioned storage space is simulated by means of the remote hardware smart card to generate a simulated storage device corresponding to the remote virtual device, for use by the remote virtual device.

Abstract: Systems, methods, and data storage devices for dynamic mode selection for hybrid MLC/SLC data storage devices are described. Storage operations at a plurality of storage devices from a host device may be processed, wherein each storage device of the plurality of storage devices comprises a plurality of partitions including multi-level cell blocks and single-level cell blocks and multi-level cell blocks may be selectively written in a single-level write operation. A usage value is determined for each partition of the plurality of partitions at each storage device of the plurality of storage devices. A storage device of the plurality of storage devices may be dynamically selected based on the usage value for single-level cell blocks of the selected storage device having available single level cell blocks. New data may then be stored at the dynamically selected storage device of the plurality of storage devices.

Abstract: A three tier memory has an upper sub block, a lower sub block, and a middle sub block. In the present disclosure, rather than precharging the upper and lower sub blocks, use is made of the middle sub block using a firmware (FW) scheme. Upon receiving a write request from a host, the FW will route the data to the middle sub block (SB1) through reverse order programming (ROP) so that the SB1 is pre-charged through the source side through the lower sub block (SB0). Once the SB1 is written, data is then routed to the SB0 and then to the upper sub block (SB2). When there is a garbage collection (GC) request, the FW will move the data from the SB2 and then erase the SB2. Then the data moves from the SB0 and SB0 is erased. Finally, the data moves from the SB1 and then SB1 is erased.

Abstract: A high-performance computing system having at least one computational group of at least one core, each computational group being associated with a computational memory, arranged to form a computational resource being utilized for performing computations, a concierge module with at least one concierge group of at least one core associated with a concierge memory arranged to form a reserved support resource being utilized for performing support functions to said computational resource.

Abstract: A memory device includes: a plurality of command and address (CA) samplers configured to receive, as a plurality of first CA signals, a command comprising a predetermined pattern via a CA bus based on an exit of a sleep mode, wherein each of the plurality of CA samplers further is configured to sample a corresponding first CA signal among the plurality of first CA signals; and a command decoder configured to check a parity error in the plurality of first CA signals sampled by the plurality of CA samplers.

Abstract: A system includes a first compute express link (CXL) storage device, a second CXL storage device, a first CXL memory device, and a CXL switch connected to the first CXL storage device, the second CXL storage device and the first CXL memory device through a CXL interface, the CXL switch configured to arbitrate communications between the first CXL storage device and the second CXL storage device, and the first CXL memory device. The first CXL memory device is configured to store first map data of the first CXL storage device and second map data of the second CXL storage device, the first CXL storage device is configured to exchange at least a portion of the first map data with the first CXL memory device through the CXL switch, and the second CXL storage device is configured to exchange at least a portion of the second map data with the first CXL memory device through the CXL switch.

Abstract: Provided are a method and apparatus for adjusting disk sequences of hard disk backplanes, a storage medium, and an electronic device. The method includes: sending a first instruction to a second hard disk backplane via a BMC, whereby the second hard disk backplane enters a low state from a high state, where a first disk sequence of a first hard disk backplane precedes a second disk sequence of the second hard disk backplane; controlling a SAS card to identify the first hard disk backplane so as to set a disk sequence of the first hard disk backplane as the first disk sequence; recovering the second hard disk backplane from the low state to the high state, controlling the SAS card to identify the second hard disk backplane in the high state so as to set a disk sequence of the second hard disk backplane as the second disk sequence.

Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.

Abstract: A computer storage device having a host interface, a controller, non-volatile storage media, and firmware. The firmware instructs the controller to: store a namespace map mapping blocks of logical block addresses in a namespace to blocks from a logical address capacity of the non-volatile storage media; adjust the namespace map to change the size of the namespace; and translate logical addresses in the namespace to physical addresses for the non-volatile storage media using the namespace map.

Abstract: An apparatus comprises associating circuitry to associate an indirect prefetch condition with a memory access request when hint information indicates that the data to be accessed in response to the memory access request is address indicating data which is to be used to generate a second address for a subsequent memory access request. A second address can be generated using the address indicating data, and a prefetch memory access request can be issued to seek to make data at the second address available in the associated cache.

Abstract: A method is provided to operate a storage device including a storage controller and a plurality of nonvolatile memory devices. A plurality of original data blocks are received at the storage controller from a host. An original parity block is generated based on the original data blocks. The original data blocks and the original parity block are stored in respective ones of the nonvolatile memory devices, wherein a first original data block of the original data blocks is stored in a first one of the nonvolatile memory devices, and wherein the original parity block is stored in a second one of the nonvolatile memory devices. A new data block corresponding to the first original data block is received at the storage controller from the host after storing the original data blocks and the original parity block. The new data block is stored in the first nonvolatile memory device.

Abstract: The present disclosure generally relates to improved address translation. Rather than fetching translated addresses using ATS/ATC, a HIM address translation search engine (HATS) is used through implementing the ATC in a layer above per an NVMe command. The HATS is an engine that will monitor pointers with untranslated addresses and will fetch the translated addresses for the pointers. Once the translated addresses are fetched for the pointer, the HATS will overwrite the untranslated address with the translated address. The HATS will then update the status of the pointers. When a translation request fails, the device will use PRI to request the translated address. During a translation request fail the device will drain any incoming requests while skipping the data transfer phase. The device will not block any other requests in a queue. Once that translated address is received through the PRI flow, the status of the pointer will be updated.

Abstract: Disclosed are a polarity inversion method and apparatus, a storage medium, and an electronic apparatus. The method includes: acquiring a product ID of a current hard disk, an identity ID of a slot of a SAS card connected to the current hard disk, and type information of the SAS card, wherein the identity ID includes a bus ID, a device ID, and a function ID; determining corresponding polarity inversion information from a preset table according to the product ID, the identity ID, and the type information, wherein different columns of the preset table are respectively configured to indicate different product IDs of the hard disk, different identity IDs of the slot, and different ID information of the SAS card; and inverting the polarity of the SAS card according to the polarity inversion information, so that the polarity which is inverted is consistent with the polarity of the current hard disk.

Abstract: A storage device is disclosed. The storage device may include storage to store data and a controller to manage reading data from and writing data to the storage. The controller may also include a receiver to receive a plurality of requests, information determination logic to determine information about the plurality of requests, storage for the information about a plurality of requests, and sharing logic to share the information with a management controller.

Abstract: Methods and apparatus for efficiently handling large data files and their updates in NAND memory. In one example, provided is a data-storage system configured to reduce the frequency of data relocations by segregating a large data file into a plurality of subfiles. The size of such subfiles is appropriately selected to reduce the probability of occurrence for host-relocation conflicts and the magnitude of write amplification, thereby enabling the data-storage system to provide better quality of service while substantially maintaining acceptable levels of other pertinent performance characteristics. In some examples, a sequence of host read-modify-write commands is handled by generating a copy of implicated subfiles in a data buffer, applying subfile updates to the copy in the data buffer in accordance with the sequence, and relocating the implicated subfiles in the NAND memory using the updated versions thereof from the data buffer.

Abstract: Various embodiments include methods and devices for implementing scaling memory frequency configuration by a computing device. Embodiments may include comparing at least a memory refresh rate, a memory size, at least one use case bandwidth of transmission between the memory and a system on chip (SoC), and a use case latency of transmission between the memory and the SoC with at least one stored memory refresh rate, at least one stored memory size, at least one stored use case bandwidth of transmission between the memory and the SoC, and at least one stored use case latency of transmission between the memory and the SoC, selecting a memory frequency based on a result of the comparison, and configuring the memory for the memory frequency. Some embodiments may include issuing an alarm indicating changing the use for the memory to be able to achieve a use case parameter.

Abstract: A method of managing sequential storage devices in a distributed storage environment including receiving, by a distributed controller, requests for performing operations, from one or more client devices in a distributed storage environment, each request including data of a client device from the one or more client devices and an identifier of a host device from one or more host devices, each of the one or more host devices being associated with one or more sequential storage devices, determining, by the distributed controller, a sequential order of the requests, based on the identifiers included in the requests, and performing, by the distributed controller in the sequential order, the operations on the one or more sequential storage devices.

Abstract: Computer-implemented methods for rebalancing a namespace range of a dispersed storage network (DSN) are provided. Aspects include calculating a namespace imbalance factor for each of a plurality of storage devices in the DSN, identifying a source storage device of the DSN having a largest namespace imbalance factor, determining a minimum namespace address, a maximum namespace address, an ideal minimum namespace address, and an ideal maximum namespace address for the source storage device, and based at least in part on a determination that the minimum namespace address is less than the ideal minimum namespace address and/or the maximum namespace address is greater than the ideal maximum namespace address, reassigning the left-deviated or right-deviated portion of the namespace range from the source storage device to its left or right neighbor storage device of the DSN.

Abstract: Methods, systems, and apparatus for management of operations in a memory system are described. An example system includes a memory device and a memory controller. The memory device includes a first buffer, a second buffer, and a third buffer including a plurality of data buffers. The memory device receives a first portion of first data of a first request from the memory controller, and stores the first portion of the first data in the first buffer or a first data buffer of the third buffer. The memory controller sends a second request to the memory device. The memory device, in response to the second request, moves the first portion of the first data from the first buffer or the first data buffer to the second buffer. The memory device performs an operation in response to the second request without using the second buffer.