Patents Examined by Ryan Bertram
  • Patent number: 12730592
    Abstract: A software RAID provisioning system includes an operating system having a software RAID multipath plugin coupled to a software RAID driver and an operating system kernel. The software RAID multipath plugin identifies first and second physical storage devices that have been configured by the software RAID driver to provide a software RAID logical storage system, and that provide a primary and secondary controller, respectively, for the software RAID logical storage system. The software RAID multipath plugin then presents a software RAID logical controller for the software RAID logical storage system to the operating system kernel. When the software RAID multipath plugin receives a command from the operating system kernel directed to the software RAID logical controller, it provides the command via an active path to the primary controller presented by the software RAID driver to cause the software RAID driver to attempt to execute the command.
    Type: Grant
    Filed: October 15, 2024
    Date of Patent: September 8, 2026
    Assignee: Dell Products L.P.
    Inventors: Nikhith Ganigarakoppal Kantharaju, Abhijit Shashikant Mirajkar, Ajay Sukumaran Nair Syamala Bai
  • Patent number: 12730579
    Abstract: A geographically distributed erasure coding system includes multiple computer readable, non-transitory storage memories capable of storing a digital dataset including multiple object blocks, where each storage memory is configured to store one or more of the object blocks of the dataset according to an erasure coding policy. The system includes one or more processors configured to implement the erasure coding policy by distributing the multiple object blocks of the dataset to the multiple storage memories according to distribution criteria of the erasure coding policy, and the distribution criteria include at least one status parameter associated with each storage memory. The multiple storage memories are geographically distributed at different locations from one another.
    Type: Grant
    Filed: June 28, 2024
    Date of Patent: September 8, 2026
    Assignee: NantCell, Inc.
    Inventor: Aaron Randolph Bassett
  • Patent number: 12724566
    Abstract: Methods, systems, and devices for memory operations are described. A memory system may write data to sequential physical addresses of the memory system based on receiving multiple write commands, where the sequential physical addresses may be associated with sequential logical addresses. Based on writing the data, the memory system may receive a read command for data stored in the memory system, where the read command may include a logical address. The memory system may determine a physical address of the memory system where the data is stored based on the received logical address, a last logical address written at the memory system, and a sequence number group associated with the last logical address. Based on determining the physical address, the memory system may read the data stored at the physical address.
    Type: Grant
    Filed: July 23, 2024
    Date of Patent: September 1, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Lalla Fatima Drissi, Doriana Tardio, Giuseppe D'Eliseo, Giuseppe Ferrari
  • Patent number: 12724714
    Abstract: A host system connected to a memory sub-system via a connection to query memory attachment capabilities of the memory sub-system in providing memory services over the connection. The memory sub-system can allocate a portion of its memory resources to provide storage services to the host system, and allocate another portion of its memory resources to provide memory services to the host system. In response to the query, the memory sub-system can provide a response containing data indicative of memory attachment capabilities of the memory sub-system. The host system can configure the memory services of the memory sub-system, such as a solid-state drive, based on the data received as a response to the query. The query and response can be implemented in the protocol over the connection for storage access, or in the protocol over the connection for memory access.
    Type: Grant
    Filed: October 25, 2023
    Date of Patent: September 1, 2026
    Assignee: Micron Technology, Inc.
    Inventor: Luca Bert
  • Patent number: 12717515
    Abstract: A data storage system includes a memory device and a controller. The memory device includes a set of planes and a wordline including a set of pages. The controller includes a first and second minimum write cache control buffer (mWCCBs), processor(s), and a memory. The memory includes instructions, that when executed the processor(s), cause the processor(s) to: determine that an amount of outstanding data of a data stream is not sufficient to occupy the set of planes; store a first portion of the outstanding data in the first mWCCB; release the first portion to the memory device; in coordination with the release of the first portion of the outstanding data, store a second portion of the outstanding data in the second mWCCB; release the second portion to the memory device; and write the first and second portions of the outstanding data to a subset of the set of pages.
    Type: Grant
    Filed: November 27, 2024
    Date of Patent: August 25, 2026
    Assignee: Microchip Technology Incorporated
    Inventors: Saswati Das, Nian Niles Yang, Srinivas Yelisetti
  • Patent number: 12717507
    Abstract: A data write method includes: obtaining a first logical address of first data; determining whether second data is stored in a storage pool, where a logical address of the second data is the same as the first logical address; and when the second data is stored in the storage pool, writing the first data to a first logical block set of the storage pool, where the first logical block set is used for storing hot data.
    Type: Grant
    Filed: April 19, 2024
    Date of Patent: August 25, 2026
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Jinsong Li, Jun Gao
  • Patent number: 12699522
    Abstract: A storage device may execute an operation of migrating valid data stored in one or more source data sections of a plurality of data sections to one or more destination data sections of the plurality of data sections in response to a request from an external device. When the valid data is migrated from the source data sections to the destination data sections, the storage device may execute an operation of writing meta data for the migrated valid data.
    Type: Grant
    Filed: October 5, 2023
    Date of Patent: August 4, 2026
    Assignee: SK hynix Inc.
    Inventors: Young Ho Ahn, Jae Youn Jang, Jin Woo Kim, Hyeong Ju Na, Yoon Won Lee, Jhu Yeong Jhin
  • Patent number: 12687963
    Abstract: Components of a distributed data object are synchronized using streamlined tracking metadata. A target component of the distributed data object is detected as it becomes available and stale. A source component that is up-to-date and that mirrors the address space of the detected target component is identified. A set of mapped address ranges and a set of unmapped address ranges of the identified source component are obtained. A mapped address range of the target component that corresponds with an unmapped address range of the source component is identified. The identified mapped address range of the target component is then synchronized with the corresponding unmapped address range of the source component. Thus, unmapped address ranges are synchronized without using tracking metadata of the source component.
    Type: Grant
    Filed: October 21, 2024
    Date of Patent: July 21, 2026
    Assignee: VMware LLC
    Inventors: Wenguang Wang, Eric Knauft, Sudheer Thokala
  • Patent number: 12681772
    Abstract: Systems and techniques for budget-based management of a cloud infrastructure are disclosed. A system monitors a cloud infrastructure for one or more trigger-action conditions associated with the cloud infrastructure. When a trigger-action condition is detected, the system determines a cloud infrastructure modification action that corresponds to the detected trigger condition. The system may apply the cloud infrastructure modification action to the cloud infrastructure. A cloud infrastructure modification action may modify one or more the workstation resources such that a rate of budget consumption is changed, for example, by pausing a resource, deleting a resource, resuming a paused resource, or changing from one resource to a different resource.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: July 14, 2026
    Assignee: Oracle International Corporation
    Inventors: Alison J. Derbenwick Miller, Pablo Selem, Sowmya Bali, Yang Jiao, Manoj Krishna Ghosh
  • Patent number: 12681642
    Abstract: Methods, systems, and devices for address mappings for random access operations are described. A portion of a L2P table may be loaded (e.g., to a buffer) upon receiving a write command (e.g., a random write command). In some instances, one or more entries (e.g., one or more mappings) included in the portion of the L2P table may be updated based on the write command. The portion of the L2P table may be maintained in the buffer during subsequent access operations, such as random read operations. The subsequent access operations may utilize the portion of the L2P table to access a memory device.
    Type: Grant
    Filed: November 16, 2023
    Date of Patent: July 14, 2026
    Assignee: Micron Technology, Inc.
    Inventors: Wenjun Wu, Huachen Li, Xiaolai Zhu, Ling Shi, Qingyuan Wang
  • Patent number: 12681855
    Abstract: A computing system comprising: a cache, comprising a virtual tag storage and a physical tag storage, where each cache line is identified for load operations by a virtual tag and for store operations by a physical tag; a cache access controller; a snoop access circuitry; and a miss controller; wherein, in response to receiving a load operation comprising a virtual address, the cache access controller: accesses the cache to perform the load operation comprising looking up a virtual tag computed using the virtual address; and upon failing to identify the virtual tag value in the virtual tag storage, provides the load operation to the miss controller; and wherein the miss controller in response to receiving the load operation from the access controller, initiates an aliasing snoop to the cache by the snoop access circuitry, the aliasing snoop comprising looking up a physical tag computed using a corresponding physical address.
    Type: Grant
    Filed: December 14, 2025
    Date of Patent: July 14, 2026
    Assignee: Next Silicon Ltd
    Inventors: Yiftach Gilad, Liron Zur, Gleb Panarin
  • Patent number: 12664100
    Abstract: An application processor, a System-on-a-Chip (SoC), and a method of operating the same are provided. The SoC includes a first processor outputting a first access address, a system bus configured to transmit an access address to a memory if the access address, which is received from the first processor corresponds to a physical address area of the memory, and to transmit the access address to other processing circuits other than the memory if the access address corresponds to a shadow physical address area other than the physical address area of the memory, and a sub-processing circuit receiving the first access address from the first processor via the system bus, converting the first access address into a second access address corresponding to the physical address area, and transmitting the second access address to the system bus to access the memory.
    Type: Grant
    Filed: September 25, 2023
    Date of Patent: June 23, 2026
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junhee Yoo, Seunghun Kim
  • Patent number: 12656970
    Abstract: A device includes a data processing engine (DPE) array having a plurality of data processing engines (DPEs) and a subsystem coupled to the DPE array. Each DPE of the plurality of DPEs is configurable to share data with one or more other DPEs of the plurality of DPEs using one or more of a plurality of data sharing techniques. The data sharing techniques include a core of a selected DPE accessing a memory module of an adjacent DPE via a memory interface of the selected DPE connected to a memory module of the adjacent DPE and the selected DPE accessing the memory module of a non-adjacent DPE using a DMA circuit and a stream switch of the selected DPE. The subsystem may be in a different die than the DPE array.
    Type: Grant
    Filed: April 15, 2024
    Date of Patent: June 16, 2026
    Assignee: Xilinx, Inc.
    Inventors: Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Tim Tuan, Ralph D. Wittig, David Clarke, Goran H. K. Bilski, Kornelis A. Vissers, Richard L. Walke, Christopher H. Dick, Zachary Dickman, Philip B. James-Roxby, Peter McColgan
  • Patent number: 12656951
    Abstract: Leveraging distinct storage tiers in a virtual storage system, including: receiving a request to write data to the virtual storage system; selecting, from amongst a plurality of tiers in the virtual storage system, a tier for receiving the data, wherein the plurality of tiers include a write-mostly tier and at least one other tier; and storing, within the selected tier within the virtual storage system, the data.
    Type: Grant
    Filed: July 15, 2024
    Date of Patent: June 16, 2026
    Assignee: EVERPURE, INC.
    Inventors: Ronald Karr, Naveen Neelakantam, Radek Aster, Joshua Freilich, Aswin Karumbunathan
  • Patent number: 12657131
    Abstract: A method for preventing cache element access in a cache. The method includes selecting a cache element represented in a global hash table, making a first determination that a shared trylock associated with the cache element can be obtained, obtaining the shared trylock based on the first determination and receiving a can inval flag; making a second determination that an exclusive trylock associated with the cache element can be obtained; obtaining the exclusive trylock based on the second determination, and invalidating, after obtaining the exclusive trylock, the cache element.
    Type: Grant
    Filed: January 23, 2025
    Date of Patent: June 16, 2026
    Assignee: Dell Products L.P.
    Inventors: Rohit K Chawla, Neha R Naik, Viral Kirtikumar Mehta, Dominick I Santangelo, Gokul Prasanna Mani
  • Patent number: 12650792
    Abstract: The present disclosure discloses a data read and write method.
    Type: Grant
    Filed: December 3, 2024
    Date of Patent: June 9, 2026
    Assignee: SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Peiqiang Dong, Lu Lu, Tiejun Liu, Jun Yang, Dafeng Han
  • Patent number: 12645366
    Abstract: Exemplary methods, apparatuses, and systems including a device health manager for managing health of a memory device. The device health manager identifies a memory device having a service life. The device health manager receives multiple requests to perform one or more computing operations. The device health manager predicts, using a machine learning model, an adjustment of the service life of the memory device using the health data. The device health manager generates a notification including the adjustment of the service life.
    Type: Grant
    Filed: April 23, 2024
    Date of Patent: June 2, 2026
    Assignee: Micron Technology, Inc.
    Inventor: Manjunath Chandrashekaraiah
  • Patent number: 12639111
    Abstract: Technology for estimating neural network (NN) power profiles includes obtaining a plurality of workloads for a compiled NN model, the plurality of workloads determined for a hardware execution device, determining a hardware efficiency factor for the compiled NN model, and generating, based on the hardware efficiency factor, a power profile for the compiled NN model on one or more of a per-layer basis or a per-workload basis. The hardware efficiency factor can be determined on based on a hardware efficiency measurement and a hardware utilization measurement, and can be determined on a per-workload basis. A configuration file can be provided for generating the power profile, and an output visualization of the power profile can be generated. Further, feedback information can be generated to perform one or more of selecting a hardware device, optimizing a breakdown of workloads, optimizing a scheduling of tasks, or confirming a hardware device design.
    Type: Grant
    Filed: July 2, 2022
    Date of Patent: May 26, 2026
    Assignee: Intel Corporation
    Inventors: Richard Richmond, Eric Luk, Lingdan Zeng, Lance Hacking, Alessandro Palla, Mohamed Elmalaki, Sara Almalih
  • Patent number: 12638987
    Abstract: Provided is a storage system. When a user registration request for a new user is received, the storage system is configured to allocate a user storage space for the new user in a plurality of storage devices, and, when a user activation request for the new user is received, the storage system is configured to generate user identification information regarding the new user, based on user credential information of the new user included in the user activation request, allocate a user area for the new user in the memory, and store the user identification information regarding the new user in the user area for the new user.
    Type: Grant
    Filed: August 12, 2024
    Date of Patent: May 26, 2026
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mungyu Bae, Sungho Yoon, Jisoo Kim, Younsung Chu
  • Patent number: 12625616
    Abstract: Techniques can include: configuring a federation to have a volume as active from only a first storage system so that hosts only sends I/O operations, directed to the first volume, to the first storage system; configuring a second storage system of the federation as inactive with respect to volume; determining, in accordance with criteria, to allow I/O operations directed to the volume to be sent to both the first and second storage systems; transitioning the second storage system, with respect to the volume, from inactive to active; and receiving, from a host at the first and second storage systems, I/O operations directed to the volume while the first and second storage systems are configured as active. The I/O operations can include a first I/O operation received at the second storage system which is redirected, by the second storage system, to the first storage system for servicing.
    Type: Grant
    Filed: August 13, 2024
    Date of Patent: May 12, 2026
    Assignee: Dell Products L.P.
    Inventors: Amitai Alkalay, Vladimir Shveidel, Lior Kamran