Patents Examined by Ryan Bertram
  • Patent number: 10725685
    Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: July 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Volodymyr Paprotski, Anthony Saporito, Timothy J. Slegel
  • Patent number: 10713081
    Abstract: Secure and efficient memory sharing for guests is disclosed. For example, a host has a host memory storing first and second guests whose memory access is managed by a hypervisor. A request to map an IOVA of the first guest to the second guest is received, where the IOVA is mapped to a GPA of the first guest, which is is mapped to an HPA of the host memory. The HPA is mapped to a second GPA of the second guest, where the hypervisor controls access permissions of the HPA. The second GPA is mapped in a second page table of the second guest to a GVA of the second guest, where a supervisor of the second guest controls access permissions of the second GPA. The hypervisor enables a program executing on the second guest to access contents of the HPA based on the access permissions of the HPA.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: July 14, 2020
    Assignee: RED HAT, INC.
    Inventors: Michael Tsirkin, Stefan Hajnoczi
  • Patent number: 10715622
    Abstract: An illustrative embodiment disclosed herein is an object store with distributed caching including a distributed cache cluster including a first cache on a first node device and a second cache on a second node device. The object store with distributed caching further includes a gateway server communicatively coupled to the distributed cache cluster. The gateway server receives a request to store an object from a client device, determines whether the object satisfies an object policy, determines whether the request indicates that the object is to be split up into a plurality of shards, and stores a first shard of the plurality of shards in the first cache and a second shard of the plurality of shards in the second cache.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: July 14, 2020
    Assignee: NUTANIX, INC.
    Inventors: Dezhou Jiang, Manik Taneja, Ranjan Parthasarathy, Xingchi Jin
  • Patent number: 10705981
    Abstract: Embodiments of the present disclosure provide a method and apparatus for providing data storage service. The method comprises: receiving a storage service template from an user, the storage service template specifying a storage service policy for the user and a service instance to launch; and providing a storage service according to the storage service template; wherein the storage service policy defines a storage function to be performed for data of the user. With the method and apparatus according to embodiments of the present disclosure, a unified solution for overall orchestration of storage functions can be provided to enable the user to customize the required storage function flexibly.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: July 7, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Layne Lin Peng, Accela Yilong Zhao, Junping Frank Zhao, Yu Cao, Xiaoyan Guo, Zhe Dong, Sanping Li
  • Patent number: 10705746
    Abstract: A memory system includes: a controller for selecting a pre-coding mode or a normal write mode in response to a host interface mode change command inputted from a host device; and a semiconductor memory device for storing, in an operating system (OS) storage area, OS data inputted from the host device in the pre-coding mode under the control of the controller.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: July 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Kwang Su Kim
  • Patent number: 10705758
    Abstract: Apparatus, methods, media and systems for multiple sets of trim parameters are described. A non-volatile memory device may comprise a first register, a second register, a multiplexer, a first set of I/O lines, each coupled to the first register and the multiplexer, each associated with a particular trim set among multiple trim sets stored in the first register, one or more second I/O lines, each coupled to the second register and the multiplexer. The multiplexer is configured to receive a control signal. The multiplexer is configured to output, based on the control signal, a particular trim set among the multiple trim sets to the second register using the one or more second I/O lines.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 7, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Tomer Tzvi Eliash, Asaf Gueta, Inon Cohen, Yuval Grossman
  • Patent number: 10705876
    Abstract: An SDS node adjusts a physical capacity included in a logical volume provided to a tenant and is to be allocated to the tenant, based on the size of data written from the tenant. An operation management system provides storage to the tenant and adjusts the provided storage to include a node and a capacity allocation and recovery system. The node provides the logical volume of the storage to the tenant, receives writing of data to the logical volume from the tenant, and writes the received data to a region included in the storage and having the physical capacity allocated to the tenant. The capacity allocation and recovery system determines a physical capacity to be interchanged based on the size of the logical volume, the size of the written data, and the physical capacity allocated to the tenant, and notifies information on the determined physical capacity to the node.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: July 7, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Souichi Takashige, Nobuhiro Maki
  • Patent number: 10705737
    Abstract: An object is to construct a storage system configured with a high degree of freedom while ensuring a certain fault tolerance. The storage system includes a plurality of nodes that process an I/O processing request of data. The node has a storage device and a processor that performs the I/O processing on the storage device. The processor constitutes a data redundancy configuration in which data stored in different storage devices is combined as a data set. A management unit for managing the storage system performs a fault tolerance calculation of calculating fault tolerance information for a failure of each component by using component information that is information of a component including at least the and the storage device, and by using data redundancy configuration information related to the data redundancy configuration, and determines a data arrangement by applying the data redundancy configuration related to the calculated fault tolerance information.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: July 7, 2020
    Assignee: HITACHI, LTD.
    Inventors: Takeru Chiba, Masakuni Agetsuma, Takahiro Yamamoto, Hiroto Ebara
  • Patent number: 10698833
    Abstract: A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Intel Corporation
    Inventors: Karthikeyan Avudaiyappan, Sourabh Alurkar
  • Patent number: 10691344
    Abstract: A first memory controller receives an access command from a second memory controller, where the access command is timing non-deterministic with respect to a timing specification of a memory. The first memory controller sends at least one access command signal corresponding to the access command to the memory, wherein the at least one access command signal complies with the timing specification. The first memory controller determines a latency of access of the memory. The first memory controller sends feedback information relating to the latency to the second memory controller.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: June 23, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Doe Hyun Yoon, Sheng Li, Jichuan Chang, Ke Chen, Parthasarathy Ranganathan, Norman Paul Jouppi
  • Patent number: 10691542
    Abstract: According to an embodiment, a storage device includes a plurality of memory nodes and a control unit. Each of the memory nodes includes a storage unit including a plurality of storage areas having a predetermined size. The memory nodes are connected to each other in two or more different directions. The memory nodes constitute two or more groups each including two or more memory nodes. The control unit is configured to sequentially allocate data writing destinations in the storage units to the storage areas respectively included in the different groups.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: June 23, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yuki Sasaki, Takahiro Kurita, Atsuhiro Kinoshita
  • Patent number: 10691345
    Abstract: A memory controller method and apparatus, which includes a modification of at least one of a first timing scheme or a second timing scheme based on information about one or more data requests to be included in at least one of a first queue scheduler or a second queue scheduler, the first timing scheme indicating when one or more requests in the first queue scheduler are to be issued to the first memory set via a first memory set interface and over a channel, the second timing scheme indicating when one or more requests in the second queue scheduler are to be issued to the second memory set via a second memory set interface and over the channel. Furthermore, an issuance of a request to at least one of the first memory set in accordance with the modified first timing scheme or the second memory set in accordance with the modified second timing scheme may be included.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: June 23, 2020
    Assignee: INTEL CORPORATION
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Mark Schmisseur
  • Patent number: 10691376
    Abstract: A computer-implemented method according to one embodiment includes identifying code word interleaved (CWI)-4 entries to be re-written to a data storage cartridge, selecting a subset of the CWI-4 entries to be included within a first CWI-4 set, where a plurality of the CWI-4 entries within the subset are associated with a single sub data set (SDS), and re-writing the first CWI-4 set to the data storage cartridge.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kevin D. Butt, Roy D. Cideciyan, Simeon Furrer, Mark A. Lantz
  • Patent number: 10691356
    Abstract: A secure storage device is connected to a computer system. The secure storage device has a memory including a domain and a subdomain storing first and second data, respectively. The computer system includes a first level hypervisor managing a first level virtual machine, which supports a first operating system, and a second level hypervisor. The second level hypervisor manages a second level virtual machine, which supports a second level operating system. A first authentication process for the first level operating system uses first profile data sent by the computer system and a portion of the first data. A second authentication process for the second level operating system uses second profile data sent by the computer system and a portion of the second data. The first data is not accessible by the second level operating system. The second data is not accessible by the first level operating system.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Klaus Werner, Joerg Schmidbauer, Jakob C. Lang
  • Patent number: 10691594
    Abstract: The present disclosure is directed to systems and methods that include cache operation storage circuitry that selectively enables/disables the Cache Line Flush (CLFLUSH) operation. The cache operation storage circuitry may also selectively replace the CLFLUSH operation with one or more replacement operations that provide similar functionality but beneficially and advantageously prevent an attacker from placing processor cache circuitry in a known state during a timing-based, side channel attack such as Spectre or Meltdown. The cache operation storage circuitry includes model specific registers (MSRs) that contain information used to determine whether to enable/disable CLFLUSH functionality. The cache operation storage circuitry may include model specific registers (MSRs) that contain information used to select appropriate replacement operations such as Cache Line Demote (CLDEMOTE) and/or Cache Line Write Back (CLWB) to selectively replace CLFLUSH operations.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 23, 2020
    Assignee: Intel Corporation
    Inventors: Vadim Sukhomlinov, Kshitij Doshi
  • Patent number: 10684961
    Abstract: External memory protection may be implemented for content addressable memory (CAM). Memory protection data, such as duplicate values for entries in a CAM or error detection codes generated from values of the entries in a CAM, may be stored in a random access memory that is separate from the CAM. When an entry in the CAM is accessed to perform a lookup or scrubbing operation, the memory protection data may be obtained from the RAM. A validation of the value of the entry may then be performed according to the memory protection data to determine whether the value is valid.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 16, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Kiran Kalkunte Seshadri, Thomas A. Volpe
  • Patent number: 10678464
    Abstract: Embodiments of the present disclosure provide methods and apparatuses for data migration of storage devices including registering at least one executing unit for data migration, each of the at least one executing unit corresponding to description file; extracting and storing information contained in the description file corresponding to each of the at least one executing unit; receiving a data migration request from a user; in response to the data migration request from the user, selecting an executing unit for data migration of the user at least based on part of the stored information contained in the description file; and scheduling an instance of the selected executing unit to execute data migration of the user. The methods or apparatuses according to embodiments of the present disclosure can implement, in a uniform and scalable manner, data migration for various formats, various performance requirements, and application scenarios.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: June 9, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Junping Frank Zhao, Layne Lin Peng, Yu Cao, Sanping Li, Zhe Dong
  • Patent number: 10678479
    Abstract: Provided are integrated circuits and methods for operating integrated circuits. An integrated circuit can include a plurality of memory banks and an execution engine including a set of execution components. Each execution component can be associated with a respective memory bank, and can read from and write to only the respective memory bank. The integrated circuit can further include a set of registers each associated with a respective memory bank from the plurality of memory banks. The integrated circuit can further be operable to load to or store from the set of registers in parallel, and load to or store from the set of registers serially. A parallel operation followed by a serial operation enables data to be moved from many memory banks into one memory bank. A serial operation followed by a parallel operation enables data to be moved from one memory bank into many memory banks.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 9, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Randy Renfu Huang, Sundeep Amirineni, Jeffrey T. Huynh
  • Patent number: 10678481
    Abstract: In various embodiments, computer-implemented techniques for improving function of in-memory processing systems via adaptively caching datasets include: identifying data stored in a distributed filesystem, the data including data to be processed by an in-memory processing application and data not to be processed by the in-memory processing application; identifying one or more partitions of the data corresponding to the data to be processed; and selectively transferring the one or more partitions from the distributed filesystem to a memory of the in-memory processing application. Corresponding systems and computer-program products are also disclosed.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: June 9, 2020
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Y. Chiu, Mohit Saxena, Erci Xu
  • Patent number: 10664193
    Abstract: A controller is configured to receive a write request from a host, and send an intermediate parity generation command corresponding to a specified address indicated by the write request to a first storage device in storage devices. The intermediate parity generation command instructs generation of an intermediate parity from new data at the specified address and old data that is updated to the new data. The intermediate parity generation command includes a first address in the memory area at which the new data is stored and a second address in the memory area for storing the intermediate parity. The first storage device is configured to receive the intermediate parity generation command, acquire the new data from the first address, generate the intermediate parity from the new data and the old data stored in the first storage device, and store the intermediate parity at the second address.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: May 26, 2020
    Assignee: HITACHI, LTD.
    Inventors: Kenta Shinozuka, Takahiko Takeda, Isamu Kurokawa, Sho Sawada