Patents Examined by Ryan Bertram
  • Patent number: 11042305
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 22, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11042323
    Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 11036411
    Abstract: Apparatuses and techniques are described for more efficiently allocating blocks of data in a memory device. The number of dedicated single-level cell (SLC) blocks which are allocated at the time of manufacture of a memory device can be reduced by transitioning a portion of the multi-level cell (MLC) blocks to an SLC mode at various times in the lifetime of the memory device. In one approach, separate counts are maintained for an MLC block in the SLC and MLC modes. The separate counts can be used to select an MLC block to transition to the SLC mode, or to select an MLC block to program. In another approach, a single count is maintained, where the SLC cycles are weighted less heavily than the MLC cycles.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 15, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Arun Thandapani, Ramkumar Ramamurthy
  • Patent number: 11029874
    Abstract: Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 8, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Yoav Markus, Alexander Bazarsky, Alexander Kalmanovich
  • Patent number: 11023153
    Abstract: A method and device for installing an operating system are provided. In an example, in a temporary system, a target RAID for installing the operating system and a unique identifier of the target RAID are determined in response to a user operation of specifying a disk array RAID. Then, a mounting point corresponding to the RAID unique identifier is found according to a correspondence between a unique identifier of a RAID and a mount point; and the target partition for installing the operating system is determined in the found mount point, and an identifier is added for the target partition. In a small system for an operating system to be installed, an installation partition and an installation disc where the installation partition is located may be determined by the identifier of the target partition, and the operating system is installed into the installation partition of the installation disc.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: June 1, 2021
    Assignee: New H3C Information Technologies Co., Ltd.
    Inventors: Yahui Di, Feng Shi, Lina Lang
  • Patent number: 11016909
    Abstract: A method for retaining data pages in a cache is disclosed. In one embodiment, such a method stores multiple data pages in a cache. The method calculates, for each data page, a cost associated with promoting the data page from persistent storage media to the cache. The cost takes into account any data transformations (decryption, decompression, etc.) that are needed to promote the data page from the persistent storage media to the cache. In certain embodiments, the cost is represented as a score that is assigned to each data page. The method retains each data page in the cache for an amount of time that is related to its cost, such that data pages with a higher cost are retained in the cache longer than data pages with a lower cost. A corresponding apparatus and computer program product are also disclosed.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: May 25, 2021
    Assignee: International Business Machines Corporation
    Inventors: Thomas C. Reed, David C. Reed
  • Patent number: 11016674
    Abstract: Techniques are directed to reading data. Such techniques involve in response to receiving a read request for the target data, determining that target data is stored in both a first storage device and a second storage device. Such techniques further involve determining at least one of reliability and access load for each of the first storage device and the second storage device. Such techniques further involve: determining, based on the at least one of the reliability and the access load, one of the first storage device and the second storage device as a target storage device so as to respond to the read request. By means of certain techniques, at least one of the access load and service lives is balanced between storage devices so as to improve the efficiency of data read and the overall performance of a storage system.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: May 25, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Hongpo Gao, Jian Gao, Xinlei Xu, Geng Han, Jianbin Kang
  • Patent number: 11010209
    Abstract: Disclosed aspects relate to speculative execution management in a coherent accelerator architecture. A first access request from a first component may be detected with respect to a set of memory spaces of a single shared memory in the coherent accelerator architecture. A second access request from a second component may be detected with respect to the set of memory spaces of the single shared memory in the coherent accelerator architecture. The first and second access requests may be processed by a speculative execution management engine using a speculative execution technique with respect to the set of memory spaces of the single shared memory in the coherent accelerator architecture.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: May 18, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pengfei Gou, Yang Liu, Yangfan Liu, Zhenpeng Zuo
  • Patent number: 10997078
    Abstract: A method for accessing a non-volatile memory comprises that an NVM controller receive a first access request from a processor and determines whether the first access request is used to access a page table. If the first access request is used to access the page table, the NVM controller obtains an AIT entry by reading a page table entry indicated by the first address information and caches the AIT entry to an AIT cache. The NVM controller monitors access of the processor to the page table, prefetches the to-be-accessed AIT entry.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: May 4, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shihai Xiao, Lei Fang, Florian Longnos
  • Patent number: 10990556
    Abstract: The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: April 27, 2021
    Assignee: GOWIN Semiconductor Corporation, Ltd.
    Inventors: Jinghui Zhu, San-Ta Kow
  • Patent number: 10990564
    Abstract: An apparatus includes a processor to: within each collection thread, assemble a row group from stored rows, generate row group metadata corresponding to the row group, and store the row group and row group metadata within a data buffer of a queue; operate the queue as a FIFO buffer; within each aggregation thread, retrieve multiple row groups and corresponding row group metadata from multiple data buffers of the queue, assemble a data set part from the multiple row groups, generate part metadata that includes the row group metadata, and transmit, to storage device(s) and/or a requesting device, the data set part and/or the part metadata; and in response to each retrieval of at least a row group from a data buffer of the queue for an aggregation thread, analyze availability of storage space within the node device to determine whether to dynamically adjust the quantity of data buffers.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 27, 2021
    Assignee: SAS INSTITUTE INC.
    Inventor: Brian Payton Bowman
  • Patent number: 10976947
    Abstract: A system includes a solid-state storage array having a plurality of solid-state storage devices and a storage controller coupled to the solid-state storage array, the storage controller including a processing device, the processing device to select a segment height based on erase block sizes of the plurality of solid-state storage devices. The processing device is further to program a data segment using the segment height to a data stripe across two or more of the plurality of solid-state storage devices and store the segment height in metadata associated with the data segment.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: April 13, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew R. Bernat, Radek Aster, Benjamin Scholbrock, Conner Haffner, Yunpeng Duan, John Adler, Tsu-Hao Chang
  • Patent number: 10977191
    Abstract: Aspects of the disclosure relate to directing and tracking translation lookaside buffer (TLB) shootdowns within hardware. One or more processors, comprising one or more processor cores, may determine that a process executing on a processing core causes one or more virtual memory pages to become disassociated with one or more previously associated physical memory addresses. The processing core which is executing that process which caused the disassociation may generate a TLB shootdown request. The processing core may transmit the TLB shootdown request to the other cores. The TLB shootdown request may include identification information, a shootdown address indicating the disassociated virtual memory page or pages which need to be flushed from the respective TLBs of the other cores, and a notification address indicating where the other cores may acknowledge completion of the TLB shootdown request.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: April 13, 2021
    Assignee: Google LLC
    Inventors: Eric Northup, Benjamin Charles Serebrin
  • Patent number: 10970258
    Abstract: Container-image layers can be managed. For example, a computing device can determine a first score for a first layer of a container image and a second score for a second layer of the container image. The computing device can determine that the first score corresponds to a first storage destination among several possible storage destinations. The computing device can also determine that the second score corresponds to a second storage destination among the possible storage destinations. The second storage destination can be different from the first storage destination. The computing device can then store (i) the first layer in the first storage destination based on the first layer being correlated to the first score, and (ii) the second layer in the second storage destination based on the second layer being correlated to the second score.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 6, 2021
    Assignee: Red Hat, Inc.
    Inventor: Huamin Chen
  • Patent number: 10970415
    Abstract: Examples of techniques for sensitive data redaction in a memory dump are described herein. An aspect includes, based on a dump of a virtual address space being triggered, receiving a primary dump corresponding to the virtual address space, the primary dump including one or more tagged memory pages. Another aspect includes identifying, by a sensitive data identification module, sensitive data that is located outside of the of the one or more tagged memory pages in the primary dump. Another aspect includes redacting data corresponding to the sensitive data and the one or more tagged memory pages to determine a redacted dump.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Purvi Sharadchandra Patel, Elpida Tzortzatos, Scott B. Compton, Hong Min
  • Patent number: 10970208
    Abstract: A memory system includes a memory device including a main memory and a cache memory that includes a plurality of cache lines for caching data stored in the main memory, wherein each of the cache lines includes cache data, a valid bit indicating whether or not the corresponding cache data is valid, and a loading bit indicating whether or not read data of the main memory is being loaded; and a memory controller suitable for scheduling an operation of the memory device with reference to the valid bits and the loading bits.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: April 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Seung-Gyu Jeong, Su-Hae Woo, Chang-Soo Ha
  • Patent number: 10963387
    Abstract: A scheme referred to as a “Region-based cache restoration prefetcher” (RECAP) is employed for cache preloading on a partition or a context switch. The RECAP exploits spatial locality to provide a bandwidth-efficient prefetcher to reduce the “cold” cache effect caused by multiprogrammed virtualization. The RECAP groups cache blocks into coarse-grain regions of memory, and predicts which regions contain useful blocks that should be prefetched the next time the current virtual machine executes. Based on these predictions, and using a simple compression technique that also exploits spatial locality, the RECAP provides a robust prefetcher that improves performance without excessive bandwidth overhead or slowdown.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Harold W. Cain, III, Vijayalakshmi Srinivasan, Jason Zebchuk
  • Patent number: 10963393
    Abstract: A method for accessing a storage system, the method may include receiving a block call, from a processor that executes an application and by a storage engine of a computer that is coupled to a storage system; generating, by the storage engine and based on the block call, a key value call; and sending the key value call to a key value frontend of the storage system.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: March 30, 2021
    Assignee: Lightbits Labs Ltd.
    Inventors: Shmuel Ben-Yehuda, Ofir Efrati, Abel Alkon Gordon, Eran Kirzner, Fabian Trumper
  • Patent number: 10965316
    Abstract: One embodiment provides a method comprising receiving an input data stream, partitioning the input data stream into a plurality of data blocks, and compressing the data blocks utilizing a plurality of processor sets. Each processor set is assigned a data block to compress. The processor sets compress in parallel to exploit inter-block parallelism. Each processor set comprises one or more processors that collaborate in compressing an assigned data block to exploit intra-block parallelism. The method further comprises writing a plurality of compressed data blocks resulting from the compressing to a storage device in encoded form.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: March 30, 2021
    Assignee: International Business Machines Corporation
    Inventors: Tim Kaldewey, Rene Mueller, Evangelia Sitaridi
  • Patent number: 10956323
    Abstract: Examples include techniques for emulating a non-volatile dual inline memory module (NVDIMM) in a computing platform using a non-volatile storage device. When a power up event occurs for the computing platform, a host memory buffer may be allocated in a system memory device and a backing store for the host memory buffer may be copied from the non-volatile storage device to the host memory buffer in the system memory device. When a power down event or a flush event occurs for the computing platform, the host memory buffer may be copied from the system memory device to the corresponding backing store for the host memory buffer in the non-volatile storage device. Thus, virtual NVDIMM functionality may be provided without having NVDIMM hardware in the computing platform.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 23, 2021
    Assignee: INTEL CORPORATION
    Inventors: Dale J. Juenemann, James A. Boyd, Robert J. Royer, Jr.