Abstract: Method and system are provided for storage allocation enhancement of microservices. A method carried out at a microservice orchestrator, includes: identifying distinct phases of a run of a microservice container; categorizing the phases of a run of a microservice container, wherein the categorization defines a predicted storage behavior of the microservice container input/output operations in the phase of the microservice container; and providing the categorization in association with the microservice container input/output operations in the phase to a storage system for use in storage allocation of the input/output operations.

Abstract: A method of communicating with a memory device through a plurality of sub-channels and a control sub-channel includes; setting a first mode or a second mode. In the first mode, writing or reading first data corresponding to a command synchronized to the control sub-channel through the plurality of sub-channels, and in the second mode, independently writing or reading second data and third data respectively corresponding to different commands synchronized to the control sub-channel through the plurality of sub-channels.

Abstract: A method is described. The method includes performing the following with a storage end transaction agent within a storage sled of a rack mounted computing system: receiving a request to perform storage operations with one or more storage devices of the storage sled, the request specifying an all-or-nothing semantic for the storage operations; recognizing that all of the storage operations have successfully completed; after all of the storage operations have successfully completed, reporting to a CPU side transaction agent that sent the request that all of the storage operations have successfully completed.

Abstract: A cold data detector circuit includes a bubble break register that is configured to detect cold data in a memory system including main memory and secondary memory. The bubble break register selectively shifts received segment addresses to fill empty slots without having to wait until the empty slots are shifted out an end slot, and may provide an indication of cold data in response to every slot of the register being filled with a different respective segment address.

Abstract: A converter module is described which handles memory requests issued by a cache (e.g. an on-chip cache), where these memory requests include memory addresses defined within a virtual memory space. The converter module receives these requests, issues each request with a transaction identifier and uses that identifier to track the status of the memory request. The converter module sends requests for address translation to a memory management unit and where there the translation is not available in the memory management unit receives further memory requests from the memory management unit. The memory requests are issued to a memory via a bus and the transaction identifier for a request is freed once the response has been received from the memory. When issuing memory requests onto the bus, memory requests received from the memory management unit may be prioritized over those received from the cache.

Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory controller may include a storage area manager and a write operation controller. The storage area manager may allocate a plurality of memory devices to a first group and a second group in response to a storage area setting command. The write operation controller may control a group selected from the first group and the second group according to a type of a write request to store write data. At least one memory devices in the first group includes memory blocks storing n data bits. At least one memory devices in the second group includes memory blocks storing m data bits.

Abstract: Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.

Abstract: A high bandwidth memory system. In some embodiments, the system includes: a memory stack having a plurality of memory dies and eight 128-bit channels; and a logic die, the memory dies being stacked on, and connected to, the logic die; wherein the logic die may be configured to operate a first channel of the 128-bit channels in: a first mode, in which a first 64 bits operate in pseudo-channel mode, and a second 64 bits operate as two 32-bit fine-grain channels, or a second mode, in which the first 64 bits operate as two 32-bit fine-grain channels, and the second 64 bits operate as two 32-bit fine-grain channels.

Abstract: Container-image layers can be managed. For example, a computing device can determine a first score for a first layer of a container image and a second score for a second layer of the container image. The computing device can determine that the first score corresponds to a first storage destination among several possible storage destinations. The computing device can also determine that the second score corresponds to a second storage destination among the possible storage destinations. The second storage destination can be different from the first storage destination. The computing device can then store (i) the first layer in the first storage destination based on the first layer being correlated to the first score, and (ii) the second layer in the second storage destination based on the second layer being correlated to the second score.

Abstract: Systems, apparatus and methods for generation of XOR signature metadata and XOR signature management are presented. In one or more embodiments, a storage device controller includes a host interface, configured to receive one or more string lines (SLs) of data from a host, the one or more SLs to be programmed into a non-volatile memory (NVM), and processing circuitry. The processing circuitry is configured to, for each of the one or more SLs, generate signature metadata and provide the signature metadata in a header of the SL. The processing circuitry is still further configured to XOR two or more of the SLs with their respective signature metadata to generate a snapshot, and write the snapshot to the NVM.

Abstract: The present disclosure generally relates to systems and methods by which a data storage device may receive data about the host system in which it is installed, and the customer associated with that system. Based upon this received data, the data storage device may modify its native operating parameters and custom functions to enable more optimal operation with the host system.

Abstract: A method for data processing, comprising updating intermediate storage information according to data to be processed and address information of the data to be processed in a first storage space, until the intermediate storage information has reached a preset size; and performing, in the first storage space, an operation corresponding to the data to be processed using the intermediate storage information, when the intermediate storage information reaches the preset size. By the above method, the computing cost for performing an operation corresponding to the data to be processed in the first storage space can be reduced, the efficiency in performing the corresponding operation can be improved, and with intermediate storage information adapted to the first storage spaces of different sizes, the number of operations on the first storage spaces can be reduced.

Abstract: Systems and methods for operating a virtual memory pool are disclosed. A network of computing machines having local real memory is provided. A translation table, which is not tightly coupled to the real memory of any one of the computing machines in the network, is generated comprising connections between locations of the various local real memories to segments of the virtual memory pool. A request is received to access a particular segment of the virtual memory pool. An address for a particular computing machine and a location in its local real memory is retrieved from the translation table. A copy of the particular segment is requested from the particular computing machine.

Abstract: Presented herein are systems and methods for backing up and restoring data from a client computing system to a provider's virtual tape library using a proxy. The proxy emulates a physical tape library that interfaces with a client's system and allowing the use of client's native tape backup commands to initiate the backup data process. The backup data is transferred into files that represent tapes in the proxy and further processed into extents in the provider's object store. The processed backup data is stored in the local cache in the object store where it is retained for future access. The backup data may also be transferred to long-term storage via a media agent that facilitate movement of the data from the local cache to secondary storage. The present disclosure also provides for creating auxiliary copies of the backed-up data using a second VTL at a second site.

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.

Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N?2)th batch of program data, N being an integer equal to or greater than 2, program an (N?1)th batch of program data into respective pages in the 3D NAND memory array, and cache an Nth batch of program data in respective space in the on-die cache as a backup copy of the Nth batch of program data.

Abstract: When performing a data migration of a first data store management system to a second data store management system, a data migration system receives a data migration rule, based on a data migration rule, converts a first data into a second data, acquires a first data model as a data model of the first data, acquires a second data model as a data model of the second data, and acquires a second program. Then, a data model conversion rule that causes the first data model to correspond to the second data model is generated based on the data migration rule, the first data model, and the second data model, and the second program is converted into a first program based on the data model conversion rule.

Abstract: Techniques for storage management may include: adding first storage devices to a pool, wherein prior to adding the first storage devices to the pool, the pool includes second storage devices with existing physical storage units (PUs) distributed across the second storage devices; and in response to adding the first storage devices to the pool, performing processing to evenly distribute the existing PUs among the pool of storage devices, said processing including: defining logical pairs of storage devices in accordance with rules; binding each of the logical pairs to a resiliency set; determining that a first PU of the existing PUs includes disk slices that span across more than a single resiliency set; andin response to determining that the first PU includes disk slices that span across more than a single resiliency set, performing second processing to restripe the first PU in accordance with a target layout.

Abstract: An example memory sub-system comprises: a memory device; and a processing device, operatively coupled with the memory device. The processing device is configured to: receive a first host data item; store the first host data item in a first page of a first logical unit of a memory device, wherein the first page is associated with a fault tolerant stripe; receive a second host data item; store the second host data item in a second page of the first logical unit of the memory device, wherein the second page is associated with the fault tolerant stripe, and wherein the second page is separated from the first page by one or more wordlines including a dummy wordline storing no host data; and store, in a third page of a second logical unit of the memory device, redundancy metadata associated with the fault tolerant stripe.

Abstract: Storage devices are capable of identifying zones for sharing parity blocks across zones. Active zones may be segregated across multiple active zones having similar zone properties, and grouped so that parity buffers can be shared. By identifying zones for optimal parity sharing, storage devices and systems can: (i) maintain independent parity for all zones during initial zone writes (i.e. during an erased state when data is written directly to pages and not to the zones), (ii) track zone write pointers and frequency of writes in the zones, (iii) segregate zones with higher correlation and group them together, (iv) utilize these groupings placed across various channels so that zones with high correlations, comprising of the zones that are written together and at the same rate, share the parity buffers, and (v) load and XOR individual parity buffers for optimal parity sharing across all zones.