Patents Examined by Ryan Bertram
  • Patent number: 11301137
    Abstract: An object is to construct a storage system with a configuration with a high degree of freedom while ensuring a certain fault tolerance. The storage system includes a plurality of nodes that process an I/O processing request of data. The node has a storage device and a processor that performs the I/O processing on the storage device. The processor constitutes a data redundancy configuration in which data stored in different storage devices is combined as a data set. A management unit for managing the storage system performs a fault tolerance calculation of calculating fault tolerance information for a failure of each component by using component information that is information of a component including at least the and the storage device, and by using data redundancy configuration information related to the data redundancy configuration, and determines a data arrangement by applying the data redundancy configuration related to the calculated fault tolerance information.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: April 12, 2022
    Assignee: HITACHI, LTD.
    Inventors: Takeru Chiba, Masakuni Agetsuma, Takahiro Yamamoto, Hiroto Ebara
  • Patent number: 11294566
    Abstract: Techniques for managing disks involve determining, based on a parameter related to a capability of a plurality of disks, a reference capability parameter for each of the plurality of disks. In addition, the techniques involve determining a used capability parameter for each of the plurality of disks. Moreover, the techniques involve determining from the plurality of disks a first disk to be adjusted, a used capability parameter of the first disk exceeds a reference capability parameter of the first disk. The techniques further involve causing data of at least one disk slice in the first disk to be moved to a second disk of the plurality of disks, such that a difference between the used capability parameter of the first disk and reference capability parameter of the first disk is below a predetermined threshold. Accordingly, a balanced operation among respective storage disks can be achieved.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 5, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Liang Huang, Ruipeng Yang, Xiaoliang Zhao, Xianlong Liu, Yunfei Chen
  • Patent number: 11294825
    Abstract: A memory system includes a memory device configured to store a piece of data in a location which is distinguished by a physical address and a controller configured to generate a piece of map data associating a logical address, inputted along with a request from an external device, with the physical address and to determine a timing of transferring the piece of map data into the external device to avoid decreasing an input/output throughput of the memory system.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: April 5, 2022
    Assignee: SK hynix Inc.
    Inventors: Eu-Joon Byun, Hye-Mi Kang, Jong-Hwan Lee, Young-Ick Cho
  • Patent number: 11294576
    Abstract: A device transmits the capabilities of the device for performing transformations on offloaded objects, to a host. The device receives an object definition command from the host, where the object definition command indicates one or more transformations to apply to an object. One or more transformations are performed on the object to generate one or more transformed objects. A completion command is transmitted to the host to indicate completion of the one or more transformations on the object.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: April 5, 2022
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Kelvin D. Green, Vasanthi Jagatha
  • Patent number: 11287994
    Abstract: Inventive aspects include a method, apparatus, and system for supporting a native key-value distributed storage system. The system includes a namenode having a KV-SSD and one or more datanodes each including one or more KV-SSDs. The system includes a client device that is communicatively coupled to the namenode and the one or more datanodes. The client device includes a native key-value storage and networking stack. Some embodiments include a hybrid block-based native key-value distributed storage system that supports both block-based files and native key-value tuples.
    Type: Grant
    Filed: January 17, 2020
    Date of Patent: March 29, 2022
    Inventors: Changho Choi, Timothy Bisson, Ke Chen
  • Patent number: 11287996
    Abstract: Techniques involve dividing a disk in RAID into a plurality of slices, and the plurality of slices include a first slice and a second slice with a first size. The techniques further involve dividing the second slice into a plurality of sub-slices, and each sub-slice in the plurality of sub-slices has a second size smaller than the first size. The techniques further involve forming a first stripe set for storing user data using the first slice and forming a second stripe set for storing metadata using the sub-slices. Such techniques enable configuring a smaller slice size for the set stripe for the metadata, and thus the granularity of storage and migration for the metadata can be reduced, and the metadata can be distributed into more disks in the RAID.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Jianbin Kang, Geng Han, Jian Gao, Jibing Dong, Xinlei Xu
  • Patent number: 11287997
    Abstract: Techniques involve determining a stripe width of an array and metadata of candidate disks available for allocating a new array, the metadata indicating a total slice number in each of the candidate disks and a number of used slices in the candidate disks. The techniques further involve determining, based on the width and the total slice number, a first number of slices in the candidate disks that are available. The techniques further involve determining, based on the number of the used slices, a second slice number in the used slices that are available; and determining, based on the first number and the second number, utilization rates of the candidate disks for the allocation for the new array. Such techniques may make the utilization rates of the candidate disks more accurate, which ensures uniform use of the respective candidate disks and improves the performance of the candidate disks.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: March 29, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Rongrong Shang, Haiying Tang, Xiaobo Zhang, Jian Gao, Zhilong Wu
  • Patent number: 11281390
    Abstract: Techniques for data migration may include: copying data of a source logical device of a source system to a target logical device of a target system; during said copying, receiving at the target system an I/O operation directed to a logical address of the target logical device and intercepting the I/O operation on the target system; determining, on the target system, to request from the source system a data page stored at the logical address; responsive to determining to request the data page stored, performing processing including: issuing a request to the source system for the data page stored at the logical address; and responsive to receiving said request, sending information from the source system to the target system, wherein the information includes the data page stored at the logical address and additional logical addresses of the source logical device at which the data page is stored.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: March 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Anton Kucherov, David Meiri
  • Patent number: 11269772
    Abstract: The present invention provides persistent memory storage engine device based on log structure and a control method, including persistent memory allocators, persistent operation logs, and a volatile index structure. The control method of log structure-based storage engine includes: allocating by persistent memory allocators, new spaces to each processor for storing updated key value pairs; organizing acquired operation information into compact log entries, and adding compact log entries into persistent operation logs according to first preset rule, where first preset rule is performing batch persistency on compact log entries from the plurality of processor cores; and updating index entries in volatile index structure to point to new key value pairs. This application fully exploits opportunity to reduce persistence overhead by redesigning log structure storage format and batch persistence mode.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 8, 2022
    Assignee: Tsinghua University
    Inventors: Jiwu Shu, Youmin Chen, Bohong Zhu, Youyou Lu
  • Patent number: 11263124
    Abstract: Devices and techniques are disclosed herein for verifying host generated physical addresses at a memory device during a host-resident FTL mode of operation to ameliorate erroneous or potentially malicious access to the memory device.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: March 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: David Aaron Palmer
  • Patent number: 11263127
    Abstract: A data storage device may include a storage and a controller for controlling the storage. The controller may include a garbage collection controller. The garbage collection controller may predict whether at least one memory block may be invalidated or not, based on a new write command with respect to a logical address having a previous write record. When the garbage collection controller predicts the invalidation of the at least one memory block, the garbage collection controller may control a garbage collection policy.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: March 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Gi Pyo Um
  • Patent number: 11249658
    Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 15, 2022
    Assignee: Rambus, Inc.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Patent number: 11244713
    Abstract: Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: February 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Corrado Villa
  • Patent number: 11237976
    Abstract: Embodiments of the disclosure relate to a memory system, a memory controller and a meta-information storage device. By providing a memory device configured to store mapping information between a logical address and a physical address, a memory controller configured to control the memory device and control a memory area in which mapping segments including some of the mapping information are stored and a meta-information storage device configured to store meta-information on the memory area, it is possible to provide a memory system, a memory controller and a meta-information storage device capable of processing a command received from a host as quickly as possible even when an SPO occurs.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: February 1, 2022
    Assignee: SK hynix Inc.
    Inventors: Hye-Mi Kang, Eu-Joon Byun
  • Patent number: 11237771
    Abstract: A method, computer program product, and computing system for receiving a plurality of updates to one or more metadata pages of a storage system, where the plurality of updates include one or more bulk updates and one or more delta updates. A transaction record may be defined. The delta updates may be written to a non-volatile log. The bulk updates may be written to a first metadata store position. The bulk updates may be written to a second metadata store position in response to writing the bulk updates to the first metadata store position. A status indicator for the transaction record may be set based upon, at least in part, writing the delta updates to the non-volatile log and one or more of writing the bulk updates to the first metadata store position and writing the bulk updates to the second metadata store position.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: February 1, 2022
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Vladimir Shveidel, Bar David
  • Patent number: 11237953
    Abstract: Systems and methods are disclosed comprising receiving first-level L2P table information from a storage system over a communication interface, maintaining a host L2P table on using the received first-level L2P table information, and providing a read command to the storage system for first data associated with a first LBA and a host L2P entry associated with the first data. The host L2P entry can include a physical address of the first LBA on the storage system according to the host L2P table and a physical address of a portion of the L2P table on the storage system associated with the first LBA. Control circuitry of the storage system can validate the physical address of the first LBA from the host L2P entry using the physical address of the portion of the host L2P table associated with the first LBA and the second-level L2P table.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Giuseppe Cariello
  • Patent number: 11237746
    Abstract: In a storage system, attributes of nodes are specified as first attribute nodes and second attribute nodes, the I/O processing in the nodes is executed as a plurality of processes including front-end I/O processing executed by any of the first attribute nodes and back-end I/O processing executed by the first and second attribute nodes having a storage device that stores data relating to the I/O processing.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: February 1, 2022
    Assignee: HITACHI, LTD.
    Inventors: Akihiro Hara, Norio Shimozono, Tomohiro Kawaguchi, Akira Deguchi
  • Patent number: 11231863
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: January 25, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Michael Sheperek, Kishore Kumar Muchherla, Mustafa N. Kaynak, Vamsi Pavan Rayaprolu, Bruce A. Liikanen, Peter Feeley, Larry J. Koudele, Shane Nowell, Steven Michael Kientz
  • Patent number: 11226771
    Abstract: The specification and drawings present a new apparatus and method for managing/configuring by the memory module controller storing operational state data for operating the memory module controller into an extended random access memory comprised in a memory module and in a host system memory of a host device during various operational modes/conditions of the memory module and the host system memory. Essentially, the memory module controller operated as a master for the data transfers as described herein. The operational state data typically comprises state information, a logical to physical (L2P) mapping table and register settings.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: January 18, 2022
    Assignee: Memory Technologies LLC
    Inventor: Kimmo J. Mylly
  • Patent number: 11226770
    Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can execute a read command that includes a first chunk of data and a second chunk of data by assigning a first read identification (RID) number to the first chunk of data and a second RID number to the second chunk of data, sending the first chunk of data and the first RID number to a host, and sending the second chunk of data and the second RID number to the host. The apparatus can be a non-volatile dual in-line memory module (NVDIMM) device.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: January 18, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Robert M. Walker, Frank F. Ross