Abstract: In some embodiments a method of addressing advanced memory buffers identifies whether a dual inline memory module includes more than one advanced memory buffer. If the dual inline memory module includes more than one advanced memory buffer, then each of the advanced memory buffers of the dual inline memory module is addressed separately, and an address is computed for a next dual inline memory module. Other embodiments are described and claimed.

Abstract: A method, computer program product and system are provided. The method, computer program product and system execute a process for determining a size of an object, the object having raw data that is operable upon by one or more physical operators. If the object is smaller than a threshold size, the object is stored in main memory of an in-memory database system. If the object is equal to or larger than the threshold size, the object is stored in a persistency of a disk storage, where storing the object in a disk storage further includes generating a global container identifier (ID) for the object, the global container ID referencing raw data of the object stored in the persistency of the disk storage.

Abstract: Example apparatus and methods reserve space in a journal using an observation based approach instead of a fixed sized approach or a worst case scenario approach. One example method receives a request to allocate space in a journal to support a file system transaction. The example method reserves an amount of space in the journal based on a pre-existing reservation size estimate. Unlike conventional systems, the estimate is not based on a worst-case scenario. The example method observes the actual amount of storage used in the journal by the file system transaction and then selectively automatically adjusts the pre-existing reservation size estimate. The estimate may slowly shrink if no overflows are encountered but may quickly grow if an overflow is detected.

Abstract: Simplification of run-time program translation for emulating complex processor pipelines is disclosed. Dynamic pipeline states are moved into a cache lookup process leaving a code translation process to deal only with static pipeline states. With dynamic pipeline states removed from the translation process, translation becomes more simple and efficient like that of a non-pipelined processor.

Abstract: A data storage system according to certain aspects manages and administers the sharing of storage resources among clients in the shared storage pool. The shared storage pool according to certain aspects can provide readily available remote storage to clients in the pool. A share list for each client may be used to determine where data is stored within the storage pool. The share list may include clients that are known to each client, and therefore, a user may feel more at ease storing the data on the clients in the storage pool. Management and administration of the storage pool and backup and restore jobs can be performed by an entity other than the client, making backup and restore more streamlined and simple for the clients in the pool.

Abstract: Systems and methods are disclosed for providing a weave sequence counter (“WSC”) for non-volatile memory (“NVM”) systems. The WSC can identify the sequence in which each page of the NVM is programmed. The “weave” aspect can refer to the fact that multiple blocks can be open for programming at once, thus allowing the pages of these blocks to be programmed in a “woven” manner. Systems and methods are also disclosed for providing a host weave sequence counter (“HWSC”). Each time new data is initially programmed to the NVM, this data can be associated with a particular HWSC. The HWSC associated with the data may not change, even when the data is moved to a new page (e.g., for wear leveling purposes and the like). The WSC and HWSC may aid in, for example, performing rollback, building logical-to-physical mappings, determining static-versus-dynamic page statuses, and performing maintenance operations (e.g., wear leveling).

Abstract: A translation lookaside buffer (TLB) configured for use in a multiple operating system environment includes a plurality of storage locations, each storage location being configured to store a page translation entry configured to relate a virtual address range to a physical address range, each page translation entry having an address space identifier (ASID) associated with an operating system. The TLB also includes flush logic configured to receive a TLB flush request from an operating system having an operating system ASID and flush only TLB page translation entries having a stored ASID that matches the operating system ASID.

Abstract: Different block management values that sequentially increase are set for a plurality of blocks to indicate active states of the blocks. For example, a first block management value “$1111” is stored in a first block, and a second management value “$1112” is stored in a second block. Thus, even when more than one block is in an active state, an updated value is read from the block that stores a larger block management value. This allows for the true updated value to be read.

Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.

Abstract: According to one embodiment, a memory system includes an application module, a storage module, and a control module. The storage module stores user data, application software configured to control operation of the application module, and management information used to manage the user data and the application software. The control module controls writing and erasing of the storage module. The control module masks information indicating an access-prohibited area included in the management information read from the storage module, the access-prohibited area includes the application software.

Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

Abstract: A memory device may comprise circuitry to determine a number of channels through which to transfer information to adjust between latency and throughput in transferring the information through the channels of a memory port.

Abstract: A method, system and computer program product for backup and restoration of data. Hash values for data blocks subject to backup are generated. After a number of hashes are accumulated, e.g., on a backup server, these hashes are sorted. Then, the hashes are compared against the hash values in the hash table corresponding to data blocks that have already been backed up. If a hash matches the hash from the hash table, a pointer to the block in the archive is written to the table of pointers to the redundant blocks. Then, this hash value is deleted from a set of the hash values. A check is made if a hash is the last in the group. If the hash is the last in the group, the remaining unique hash values are written into the hash table. Otherwise, the next hash is selected from the group. The redundant data blocks are discarded and only unique data is backed up.

Abstract: During execution of an application that accesses a shared memory, a security component may, based on an indication from a performance monitor, determine that the application is carrying out a timing side-channel attack. The performance monitor may trigger an interrupt if a pre-determined number of cache line flushes is executed, after which the security component may inspect program instructions of the executing application to determine whether those instructions are likely being used in such an attack. In response to determining that an attack is under way, the security component may take action to mitigate or curtail the attack. The security component may modify the program instructions or page mapping of the executing application to make accesses to portions of the shared memory targeted by the cache line flushes predictable or consistent (e.g., by replacing the instructions with traps, removing them, or inserting instructions immediately before or after them).

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.

Abstract: A method and apparatus to reduce unnecessary write backs of cached data to a main memory and to optimize the usage of a cache memory tag directory. In one embodiment of the invention, the power consumption of a processor can be saved by eliminating write backs of cache memory lines that has information that has reached its end-of-life. In one embodiment of the invention, when a processing unit is required to clear one or more cache memory lines, it uses a write-zero command to clear the one or more cache memory lines. The processing unit does not perform a write operation to move or pass data values of zero to the one or more cache memory lines. By doing so, it reduces the power consumption of the processing unit.

Abstract: A transactional memory system salvages hardware lock elision (HLE) transactions. A computer system of the transactional memory system records information about locks elided to begin HLE transactional execution of first and second transactional code regions. The computer system detects a pending cache line conflict of a cache line, and based on the detecting stops execution of the first code region of the first transaction and the second code region of the second transaction. The computer system determines that the first lock and the second lock are different locks and uses the recorded information about locks elided to acquire the first lock of the first transaction and the second lock of the second transaction. The computer system commits speculative state of the first transaction and the second transaction and the computer system continues execution of the first code region and the second code region non-transactionally.

Abstract: A computer-implemented method of caching data in a managed runtime computing environment can include loading source data and comparing content of the source data with at least one of a plurality of cache entries. Each cache entry can include a representation of previously received source data and a transformation of the previously received source data. A transformation for the source data from a cache entry can be selected or a transformation for the source data can be generated according to the comparison. The transformation for the source data can be output.

Abstract: A virtual storage migration method is provided, including: starting a data migration process, and copying, from a source storage device to a destination storage device, a data block in a virtual disk to be migrated; when a VM front-end I/O read request is received, directly reading, corresponding data from the source storage device; when a VM front-end I/O write request is received, determining whether a migration data block that corresponds to the write request is being migrated, if yes, executing a write operation that corresponds to the write request after the migration of the migration data block is completed, if no, executing a write operation that corresponds to the write request; and after all the data blocks in the virtual disk to be migrated are copied to the destination storage device, stopping the data migration, and switching the virtual disk from the source storage device to the destination storage device.