Abstract: An integrated circuit (IC) module comprising at least one memory mapped resource, at least one port arranged to be coupled to a further IC module, and an address decoding component. Upon receipt of a resource access request by the IC module, the address decoding component is arranged to extract at least one position parameter from an address field of the received resource access request, determine if the at least one position parameter indicates a target resource as residing within the IC module, and if it is determined that the at least one position parameter indicates the target resource as not residing within the IC module, modify the at least one position parameter to represent a change of one position and forward the resource access request with the modified position parameter over the port to the further IC module.

Abstract: In at least some embodiments, a cache memory of a data processing system receives a speculative memory access request including a target address of data speculatively requested for a processor core. In response to receipt of the speculative memory access request, transactional memory logic determines whether or not the target address of the speculative memory access request hits a store footprint of a memory transaction. In response to determining that the target address of the speculative memory access request hits a store footprint of a memory transaction, the transactional memory logic causes the cache memory to reject servicing the speculative memory access request.

Abstract: A cache storage method includes providing a storage cache cluster, comprising a plurality of cache storage elements, for caching I/O operations from a plurality of virtual machines associated with a corresponding plurality of virtual hard disks mapped to a logical storage area network volume or LUN. Responsive to a cache flush signal, flush write back operations are performed to flush modified cache blocks to achieve or preserve coherency. The flush write back operations may include accessing current time data indicative of a current time, determining a current time window in accordance with the current time, determining a duration of the current time window, and identifying a current cache storage element corresponding to the current time window. For a duration of the current time window, only those write back blocks stored in the current cache storage element are flushed.

Abstract: In distributed storage environments (e.g., VPLEX®, from EMC Corporation) a director may be added while the distributed data is being replicated. However, the new director may have new splitters that do not know what to replicate and how to handle new I/Os. If I/Os are missed or lost, that information is gone forever and may be recovered only by a full resync of the volume. However, example embodiments of the present invention overcome these and other deficiencies by allowing adding a director and new splitters without interruption of the replication. Example embodiments of the present invention provide a method, an apparatus and a computer-program product for adding a director to storage with network-based replication without data resynchronization. The method includes obtaining distributed storage system node configuration information and performing replication in a network-based replication system according to the configuration information.

Abstract: According to one embodiment, a memory system perform a first write operation for writing data to a non-volatile memory by a first write method for writing multi-bit information per memory cell. When a power loss event occurs while the data is written, the memory system calculates a remaining time period required to complete write of an unwritten portion of the data. When the remaining time period is longer than a time period required to write the whole of the data by a second write method for writing one-bit information per memory cell, the memory system performs a second write operation for writing the whole of the data by the second write method in place of the first write operation.

Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

Abstract: A data erasing method of the present disclosure is a data erasing method for erasing data stripe-recorded in a plurality of write-once optical discs constituting a redundant arrays of inexpensive disks (RAID) system and each including a plurality of data recording blocks and a redundant data block. In the data erasing method, alternate recording of at least one target block and the redundant data block is performed in a predetermined alternate area. The target block is one of the data recording blocks in which target data as erase target data is recorded. The target block is overwritten such that the target data is not correctly read.

Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a cache that is controlled by a cache controller. The cache controller is configured to replace cachelines in the cache based on a replacement scheme that prioritizes the replacement of cachelines that are less likely to cause roll back of a transaction of the microprocessor.

Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)-way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.

Abstract: Atomically accumulating memory updates in a computer system configured with an accumulator that is memory mapped. The accumulator includes an accumulator memory and an accumulator queue and is configured to communicatively couple to a processor. Included is receiving from the processor, by the accumulator, an accumulation request. The accumulation request includes an accumulation operation identifier and data. Based on determining, by the accumulator, that the accumulator can immediately process the request, immediately processing the request. Processing the request includes atomically updating a value in the accumulator memory, by the accumulator, based on the operation identifier and data of the accumulation request. Based on determining, by the accumulator, that the accumulator is actively processing another accumulation request, queuing, by the accumulator, the accumulation request for later processing.

Abstract: A chassis management controller includes a root file system, a shared memory, a daemon process module, and an interposer library. The root file system includes a plurality of directories associated with firmware applications of the chassis management controller. The daemon process module is configured to read the parameters of the directories, and to create, in the shared memory, a table including parameters of the directories. The interposer library is configured to intercept an input/output library call for an operation associated with one of the firmware applications, to read table entries associated the one or the firmware applications, to determine whether the operation associated with the input/output library call would result in an over-allocation of a parameter in the entries of the table, and if the operation would not result in the over-allocation, pass the output operation to a standard system library, otherwise to return an out of space error message.

Abstract: Various embodiments provide for a system that prefetches data from a main memory to a cache and then evicts unused data to a lower level cache. The prefetching system will prefetch data from a main memory to a cache, and data that is not immediately useable or is part of a data set which is too large to fit in the cache can be tagged for eviction to a lower level cache, which keeps the data available with a shorter latency than if the data had to be loaded from main memory again. This lowers the cost of prefetching useable data too far ahead and prevents cache trashing.

Abstract: A computer system that is programmed with virtual memory accesses to physical memory employs multi-bit counters associated with its page table entries. When a page walker visits a page table entry, the multi-bit counter associated with that page table entry is incremented by one. The computer operating system uses the counts in the multi-bit counters of different page table entries to determine where large pages can be deployed effectively. In a virtualized computer system having a nested paging system, multi-bit counters associated with both its primary page table entries and its nested page table entries are used. These multi-bit counters are incremented during nested page walks. Subsequently, the guest operating systems and the virtual machine monitors use the counts in the appropriate multi-bit counters to determine where large pages can be deployed effectively.

Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, and configured to store, for at least some of the data blocks, corresponding historical information about prior removal of one or more data units from that data block, the removal affecting at least some addresses of data units in that data block. The system is configured to perform at least one operation that accesses at least a first data unit stored in a first data block according to address information interpreted based on any stored historical information corresponding to the first data block.

Abstract: An architecture for improved memory access in asymmetric memories provides a set of shared row buffers that may be freely allocated between slow and fast memory banks of the asymmetric memory. This permits allocation of row buffers dynamically between the slow and fast memory banks to improve execution speeds and also permits a lightweight memory swap procedure for moving data between the slow and fast memory banks with low processor and memory channel overheads.

Abstract: Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.

Abstract: According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus includes a first control circuit configured to send a delete notification to the nonvolatile storage device to invalidate data in a first logical address area when read data corresponding to the first logical address area is the same as data expressed by a first function. The nonvolatile storage device include a nonvolatile storage medium, a management table configured to associate a logical address corresponding to valid data for the nonvolatile storage device with a physical address, and a second control circuit configured to update the management table to invalidate a logical address designated by the delete notification, and to send the data expressed by the first function to the information processing apparatus when a logical address included in a read instruction received from the information processing apparatus is invalid.

Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform one or more operations with respect to data units, the operations including a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit, with the second data block having the same size as the first data block.

Abstract: A method for managing workloads in a multiprocessing computer system is disclosed. Initially, a set of affinity domains is defined for a group of processor cores, wherein each of the affinity domains includes a subset of the processor cores. An affinity measure is defined to indicate that a given workload should be moved to a smaller affinity domain having fewer processor cores. A performance measure is defined to indicate the performance of a given workload. A given workload is determined based on the affinity measure and the performance measure. In response to a determination that a given workload should be moved to a smaller affinity domain based on the affinity measure, the given workload is moved to a smaller affinity domain. In response to a determination that there is a reduction in performance based on the performance measure, the given workload is moved to a larger affinity domain.

Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.