Abstract: A counter of a primary memory module provides a count indicative of the number of times the primary memory module has ever been read/written by a processor. With the count, an operating mode of the primary memory module is evaluated to optimize memory allocation performed by the data processing system, adjust the operating mode of the primary memory module, and send a warning message to a user, for example.

Abstract: A computing device includes an interface configured to interface and communicate with a dispersed storage network (DSN), a memory that stores operational instructions, and a processing module operably coupled to the interface and memory such that the processing module, when operable within the computing device based on the operational instructions, is configured to perform various operations. For example, the computing device monitors storage unit (SU)-based write transfer rates and SU-based write failure rates associated with each of the SUs for a write request of encoded data slices (EDSs) to the SUs within the DSN. The computing device generates and maintains a SU write performance distribution based on monitoring of the SU-based write transfer rates and the SU-based write failure rates and adaptively adjusts a trimmed write threshold number of EDSs and/or a target width of EDSs for write requests of sets of EDSs to the SUs within the DSN.

Abstract: Systems, apparatuses, and methods for sorting memory pages in a multi-level heterogeneous memory architecture. The system may classify pages into a first “hot” category or a second “cold” category. The system may attempt to place the “hot” pages into the memory level(s) closest to the systems' processor cores. The system may track parameters associated with each page, with the parameters including number of accesses, types of accesses, power consumed per access, temperature, wearability, and/or other parameters. Based on these parameters, the system may generate a score for each page. Then, the system may compare the score of each page to a threshold. If the score of a given page is greater than the threshold, the given page may be designated as “hot”. If the score of the given page is less than the threshold, the given page may be designated as “cold”.

Abstract: Systems and methods for enabling disk image operations in conjunction with snapshot locking. An example method may include: attaching a first snapshot to a first virtual machine the first snapshot being stored within a disk image, generating, in view of the first snapshot, a second snapshot, the second snapshot being stored within the disk image, attaching the first snapshot to a second virtual machine, and causing the first snapshot to be locked in view of the second virtual machine performing one or more operations on the first snapshot, wherein the first virtual machine performs one or more operations on the second snapshot concurrent with the locking of the first snapshot.

Abstract: A system on chip (SoC) may include a nonvolatile ferroelectric random access memory (FRAM). A random number may be created by applying operating power to the ferroelectric random access memory (FRAM) device and reading a sequence of virgin memory locations within the FRAM device to produce the random number sequence. The sequence of virgin memory locations had previously never been written. The random number may be produced during an initial boot of the SoC, for example. Alternatively, the random number may be saved by a test station during testing of the FRAM device after fabrication of the FRAM device. A memory test of the FRAM may then be performed, after which the random number may be stored in a defined location in the FRAM.

Abstract: A memory card is attached to a host device, and includes a data control circuit which transfers data with respect to the host device in synchronism with a rise edge and a fall edge of a clock signal.

Abstract: A solid state drive (SSD) employing a redundant array of independent disks (RAID) scheme includes a flash memory chip, erasable blocks in the flash memory chip, and a flash controller. The erasable blocks are configured to store flash memory pages. The flash controller is operably coupled to the flash memory chip. The flash controller is also configured to organize certain of the flash memory pages into a RAID line group and to write RAID line group membership information to each of the flash memory pages in the RAID line group.

Abstract: A system, methods, and apparatus for determining memory distribution across multiple non-uniform memory access processing nodes are disclosed. An apparatus includes processing nodes, each including processing units and main memory serving as local memory. A bus connects the processing units of each processing node to different main memory of a different processing node as shared memory. Access to local memory has lower memory access latency than access to shared memory. The processing nodes execute threads distributed across the processing nodes, and detect memory accesses made from each processing node for each thread. The processing nodes determine locality values for the thread that represent the fraction of memory accesses made from the processing nodes, and determine processing time values for the threads for a sampling period. The processing nodes determine weighted locality values for the threads, and determine a memory distribution across the processing nodes based on the weighted locality values.

Abstract: Techniques to back up a cluster shared volume (CSV) are disclosed. In various embodiments, a snapshot of the cluster shared volume is stored persistently on the cluster shared volume itself. A task to back up a corresponding assigned portion of the snapshot is assigned to each of one or more cluster servers available to participate in backing up the cluster shared volume. The cluster servers have shared access to the snapshot as stored on the cluster shared volume, and each is configured to perform the task assigned to it in parallel with any other cluster servers assigned to back up other portions of the same cluster shared volume snapshot. The respective assigned tasks are monitored to completion.

Abstract: Techniques to optimize use of the available capacity of a backup target storage device are disclosed. In various embodiments, a current capacity of a target system to which backup data is to be streamed to handle additional streams is determined dynamically, at or near a time at which a backup operation is to be performed. One or more backup parameters of the backup operation is/are set dynamically, based at least in part on the dynamically determined current capacity of the target system.

Abstract: A computing system includes a parent partition, child partitions, a hypervisor, shared memories each associated with one of the child partitions, and trigger pages each associated with one of the child partitions. The hypervisor receives a system event signal from one of the child partitions and, in response to receiving the system event signal, accesses the trigger page associated with that child partition. The hypervisor determines whether the trigger page indicates whether data is available to be read from the shared memory associated with the child partition. The hypervisor can send an indication to either the parent partition or the child partitions that data is available to be read from the shared memory associated with the child partition if the hypervisor determines that the trigger page indicates that data is available to be read from the shared memory associated with the child partition.

Abstract: A transaction manager for handling operations on data in a storage system provides a system for executing transactions that uses a versioned tuple cache to achieve fast, abortable transactions using a redo-only log. The transaction manager updates an in-memory key-value store and also attaches a transaction identifier to the tuple as a minor key. Opportunistic locking can be accomplished due to the low cost of aborting transactions.

Abstract: In at least some embodiments, a cache memory of a data processing system receives a speculative memory access request including a target address of data speculatively requested for a processor core. In response to receipt of the speculative memory access request, transactional memory logic determines whether or not the target address of the speculative memory access request hits a store footprint of a memory transaction. In response to determining that the target address of the speculative memory access request hits a store footprint of a memory transaction, the transactional memory logic causes the cache memory to reject servicing the speculative memory access request.

Abstract: An apparatus, method, and computer program for maintaining access times in a data processing system, wherein the data processing system comprises a plurality of storage devices, the apparatus including: a receive component, for receiving a command or an availability message, wherein an availability message indicates whether the storage device is available; an evaluate component for evaluating a plurality of first relationships between the storage devices and a plurality of first values, wherein each of the first values indicates whether a related storage device is a redundant; a send component, for sending a power message to one or more of the storage devices; and an update component for updating a second relationship between the redundant storage device and a plurality of second values, wherein each of the second values indicates whether a related redundant storage device is available.

Abstract: In an apparatus including a plurality of integrated circuit chips, it makes it possible not to connect a ROM to all integrated circuit chips. Each chip incorporates a processor, and has terminal for connecting with a ROM and a RAM. The chip includes a communication unit communicating with another integrated circuit chip, and a reset controller which includes a register storing initial data setting for the processor in a reset state, and selects, based on a logical level of an external terminal, between whether to provide the data of the register to a reset terminal of the processor and whether to provide an external signal to the reset terminal of the processor.

Abstract: Devices, systems and methods are provided for writing, by a plurality of computing resources, to contiguous memory addresses of memory that supports random access, without having to specify actual write addresses of the memory.

Abstract: A calibration memory control method of an ECU connected to an external calibration device may include receiving a download command from the external calibration device, checking a sub reference page corresponding to the download command, determining whether a sub working page corresponding to the checked sub reference page is allocated, allocating the sub working page corresponding to the checked sub reference page to a RAM region upon determining that the sub working page is not allocated, and copying data stored in the checked sub reference page to the allocated sub working page. As such, according to the present invention, restrictive memory resources may be efficiently used for calibration.

Abstract: A data storage system according to certain aspects manages and administers the sharing of storage resources among clients in the shared storage pool. The shared storage pool according to certain aspects can provide readily available remote storage to clients in the pool. A share list for each client may be used to determine where data is stored within the storage pool. The share list may include clients that are known to each client, and therefore, a user may feel more at ease storing the data on the clients in the storage pool. Management and administration of the storage pool and backup and restore jobs can be performed by an entity other than the client, making backup and restore more streamlined and simple for the clients in the pool.

Abstract: A mechanism is provided for managing memory of a runtime environment executing on a virtual machine. A balloon agent that is part of a runtime environment is configured to coordinate inflations of a memory balloon within a heap of” the runtime environment and an out-of-heap overflow balloon, particularly in situations where a hypervisor needs to reclaim more memory from the runtime environment than the runtime environment is able to give up. The balloon agent may slowly free out-of-heap balloon memory, which may cause an increase of a target size for the balloon agent, which in turn inflates the memory balloon inside the heap of the runtime environment.

Abstract: A system for managing storage of data units includes a data storage system configured to store multiple data blocks, at least some of the data blocks containing multiple data units, with at least a group of the data blocks being stored contiguously, thereby supporting a first read operation that retrieves data units from at least two adjacent data blocks in the group. The system is configured to perform two or more operations with respect to data units. The operations include: a second read operation, different from the first read operation, that retrieves a data unit to be read based at least in part on an address of a data block containing the data unit to be read, and a delete operation that replaces a first data block containing a data unit to be deleted with a second data block that does not contain the deleted data unit.