Abstract: A quadrature clock generator includes a variable delay clock generator configured to receive a first clock and a third clock and output a second clock and a fourth clock in accordance with a control signal, wherein the first clock and the third clock are substantially the same but offset in timing by one half of the period; a quadrature phase error detector configured to receive the first clock, the second clock, the third clock, and the fourth clock and output a first phase detection signal and a second phase detection signal, wherein the first phase detection signal represents a relative timing between the first clock and the second clock and the second phase detection signal represents a relative timing between the second clock and the third clock; and an amplifier configured to amplify a difference between the first phase detection signal and the second phase detection signal into the control signal.

Abstract: An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

Abstract: Aspects of the disclosure are directed to clock management. In accordance with one aspect, a clock management apparatus for built-in self-test (BIST) circuitry includes a plurality of local clock controllers; a plurality of clock generators coupled to the plurality of local clock controllers; a master clock controller coupled to the plurality of clock generators; an X-tolerant logical built-in self test (XLBIST) circuit coupled to the master clock controller; and a test access port (TAP) coupled to the XLBIST circuit.

Abstract: Various embodiments relate to digital demodulation for wireless power transmission. A wireless power transmitter includes a transmitter coil and a controller. The transmitter coil is configured to wirelessly couple to a receiver coil of a wireless power receiver to transfer power to the wireless power receiver responsive to a coil current applied to the transmitter coil. The wireless power receiver is configured to modulate at least one electrical condition of the wireless power receiver to modulate the coil current at the transmitter coil. The controller is configured to sample one or more electrical signals of the wireless power transmitter, and digitally demodulate the sampled one or more electrical signals to obtain a communication received from the wireless receiver responsive to the modulation of the at least one electrical condition of the wireless power receiver.

Abstract: A method for operating an IGBT includes determining a maximum stationary reverse bias required for operation of the IGBT, determining a first removal charge, the removal of which at the gate of the IGBT causes an electric field strength that enables the IGBT to accept the maximum stationary reverse bias during stationary blocking, determining a second removal charge, the removal of which at the gate causes an electric field strength that leads to a dynamic avalanche, and, when the IGBT is switched off, removing from the gate during a charge removal duration a removal charge that is greater than the first removal charge and smaller than the second removal charge.

Abstract: Power systems and methods of using the same to deliver power. A power system referenced herein can include a housing capable of attaching to a workstation, one or more cradles or mounting fixtures to receive at least one energy storage device, electronic circuitry to communicate status of the at least one energy storage device, state of charge of the at least one energy storage device, and/or overall health of the at least one energy storage device, and one or more electrical connectors to allow the at least one energy storage device to charge and/or discharge and communicate with the electronic circuitry, with said housing having an internal power supply and charge circuitry, said power supply capable of receiving input power from an external AC or DC power source; wherein the power system is configured to deliver power to the workstation.

Abstract: A power supply control system includes a power supply controller configured to selectively supply electrical power to a venue; and a booking controller located remotely from the venue, the booking controller configured to maintain third party booking information, wherein the power supply controller is configured to control the supply of electrical power based on the third party booking information. A power supply controller and booking controller for the power supply control system are also provided.

Abstract: A utility power regulation system includes a power converter configured to regulate one or more of a voltage and a power factor at the primary side of a step-up transformer, or at a load electrically connected to a load feeder line, based on an estimated primary-side line voltage signal. The system includes a voltage estimation circuit configured to estimate the primary-side line voltage signal from one or more signals received from a secondary-side voltage sensor, regulator line current signal, and a primary-side load feeder-line current sensor.

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

Abstract: Controlling an energy storage system includes providing one or more constraints to an optimization problem algorithm, determining by the optimization problem algorithm a DC bus voltage value that results in an minimum total power dissipation for the plurality of power converters, calculating a respective control variable for each of the respective plurality of power converters based on the determined DC bus voltage value, and generating control processor executable instructions to implement control of each of the plurality of power converters to achieve the calculated respective control variable. A system for implementing the method and a non-transitory computer-readable medium are also disclosed.

Abstract: A circuit and method for controlling charge injection in a circuit are disclosed. In one embodiment, the circuit and method are employed in a semiconductor-on-insulator (SOI) Radio Frequency (RF) switch. In one embodiment, an SOI RF switch comprises a plurality of switching transistors coupled in series, referred to as “stacked” transistors, and implemented as a monolithic integrated circuit on an SOI substrate. Charge injection control elements are coupled to receive injected charge from resistively-isolated nodes located between the switching transistors, and to convey the injected charge to at least one node that is not resistively-isolated. In one embodiment, the charge injection control elements comprise resistors. In another embodiment, the charge injection control elements comprise transistors.

Abstract: A Schmitt trigger voltage comparator circuit is provided including a voltage reference input, a current source having a first voltage controlled current source connected to the voltage reference input and a second voltage controlled current source connected to a signal input for converting the signal input to a input current and the voltage reference input to a reference current, a current mirror having an input connected to the output of the first voltage controlled current source configured and arranged to invert the direction of the first current and an output of the current mirror connected to the output of the second voltage controlled current source, and a sequence controller for generating digital signals to control a first plurality of switches and a second plurality of switches. The first plurality of switches control the first and second voltage controlled current sources and the second plurality of switches control the current mirror.

Abstract: A delay circuit is disclosed. The delay circuit is coupled to a relay switch that is contained in a power conversion device. When an electronic device having the power conversion device is operated in a sleep mode, the delay circuit applies a time delaying process to a power signal that is transmitted to the relay switch, such that a rising time of each of switch-on pulses contained by the power signal is delayed for a specific time. The specific time is set to be longer than a pulse width of each of power-on pulses contained by a power switching signal of the power conversion device. As such, when the electronic device is operated in the sleep mode, switching actions of the relay switch is properly controlled, thereby making the power conversion device not produce noise. Moreover, the service life of the relay unit is also extended.

Abstract: Systems and apparatuses include a control circuit and a switching circuit. The control circuit is structured to communicate with a real-time-clock battery and to selectively communicate with a vehicle battery. The control circuit is structured in an OFF arrangement when a wake supply voltage is received from the vehicle battery and in an ON arrangement when no wake supply voltage is received. The switching circuit is structured to provide communication between the real-time-clock battery and a real-time-clock power pin of a controller with a voltage drop of about 0.1 volts or less when the control circuit is in the ON arrangement and to inhibit communication between the real-time-clock battery and the real-time-clock power pin when the control circuit is in the OFF arrangement.

Abstract: A method for optimizing power of a ranging sequence includes counting at least one cycle of a first clock during a Crystal Oscillator (XO)-mode to generate a first cycle count. A second clock is activated at an end of the XO-mode. The first cycle count is converted into a fractional correction value by multiplying the first cycle count by a ratio of a second period of the second clock divided by a first period of the first clock. A first alignment of the first clock to the second clock is determined at a beginning of the XO-mode. A second alignment of the first clock to the second clock is determined at the end of the XO-mode. An adjusted cycle count is determined by summating the fractional correction value with a summation of the first alignment and the second alignment divided by the first period.

Abstract: A measuring device and a measuring method are provided. The measuring device includes an oscillating circuit, a time average frequency-frequency lock loop, and a digital signal processing circuit. The oscillation circuit includes an element to be measured and is configured to output a signal having an oscillation frequency correlated with an element value of the element to be measured. The time average frequency-frequency lock loop is configured to receive the signal output by the oscillation circuit and output a frequency control word correlated with the oscillation frequency. The digital signal processing circuit is configured to read the frequency control word output by the time average frequency-frequency lock loop and obtain the element value of the element to be measured according to the read frequency control word. The measuring device is easy to integrate, has small volume, low power consumption, and high reliability, and can achieve high-precision measurement.

Abstract: A timing circuit can include: a low-precision clock source configured to generate a low-precision clock signal; a high-precision clock source configured to intermittently generate a high-precision clock signal; and a cycle conversion circuit configured to count the pulses of the high-precision clock signal and the low-precision clock signal during a same period, and to obtain a conversion cycle according to count results and a rated cycle of the high-precision clock signal.

Abstract: In one embodiment, a droop detector circuit, comprising: a reference oscillator; plural delay lines configured to receive signals from the reference oscillator; and logic configured to detect droop in a voltage regulator based on an output of the voltage regulator and outputs of each of the plural delay lines.

Abstract: Disclosed is a level shifter. The level shifter includes a level shifting circuit, a first adjusting circuit, and a second adjusting circuit. The level shifting circuit determines whether to output a first current from a supply voltage line to an output node based on a voltage level of a first node and determines whether to output a second current from the supply voltage line to a third node based on a voltage level of a second node. The first adjusting circuit blocks an output of a third current from the third node to the first node when a clock signal having a first voltage level is received. The second adjusting circuit outputs a fourth current from the first node to a ground voltage line when the clock signal having the first voltage level is received.

Abstract: A reconfigurable all-digital temperature sensor includes a NAND gate and several delay units, the NAND gate comprises two input terminals and an output terminal, one input terminal is used for external starting control signal; a plurality delay units are connected in series, the input end of the first delay unit is connected to the output terminal of the NAND gate, and the output end of the last delay unit is connected to another input terminal of the NAND gate, thereby forming a ring oscillator structure; each delay unit includes a leakage-based inverter and a Schmitt trigger, and the output end of the leakage-based inverter is connected to the input end of the Schmitt trigger. The reconfigurable all-digital temperature sensor can realize the conversion of temperature-leakage-frequency based on the ring oscillator structure in the temperature range of ?40˜125° C., thereby reducing the design complexity and achieving high accuracy.