Patents Examined by Ryan Jager
  • Patent number: 11146264
    Abstract: An electric circuit for testing a power-on reset circuit. The electric circuit including a comparator, which is configured to detect an undervoltage for an input voltage to be compared to a reference voltage and to output an output signal, a first noise filter for filtering out noise from the output signal received as a first input signal for a first time period and for outputting a first filtered output signal of a second noise filter for filtering out noise from a second input signal for a second time period, and for outputting a second filtered output signal, and a digital part having an OR gate for the logical linkage of a first filtered output signal and a second filtered output signal for the output of a power-on reset signal.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: October 12, 2021
    Assignee: Robert Bosch GmbH
    Inventor: Harish Balasubramaniam
  • Patent number: 11146262
    Abstract: A reference voltage generator is disclosed. The reference voltage generator may include an operational transconductance amplifier (OTA), a bias generator, a first flipped voltage follower, a bias filter, a control signal filter, and a second flipped voltage follower. The OTA and the first flipped voltage follower may generate a control signal based on a reference voltage and a bias voltage from the bias generator. The bias filter may filter the bias voltage and the control signal filter may filter the control signal. The second flipped voltage follower may generate the output voltage based on the filtered bias voltage and the filtered control signal.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: October 12, 2021
    Assignee: Xilinx, Inc.
    Inventors: Yipeng Wang, Kee Hian Tan
  • Patent number: 11146165
    Abstract: For grid-connected power converter control, a method estimates a d-axis grid voltage from a d-axis reference current modified with a d-axis current and a q-axis current modified with a filter inductive reactance. The method generates a q-axis current error from a direct current (DC) voltage input and a DC bus voltage. The method estimates an observer q-axis grid voltage from a q-axis voltage output. The q-axis grid voltage observer estimates the q-axis grid voltage in a direct/quadrature (dq) reference frame equivalent to an ABC to DQ reference frame transform. The method determines a d-axis voltage output as a function of a d-axis current error and a q-axis current modified with a filter inductive reactance. The method determines a q-axis voltage output as a sum of the q-axis current controller output and the observer q-axis grid voltage.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: October 12, 2021
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Lei Jin, Haihui Lu, Ahmed S. Mohamed Sayed Ahmed, Rob J Miklosovic
  • Patent number: 11137812
    Abstract: Dedicated circuitry may monitor a processor supply voltage and provide additional power on a temporary nano-second scale basis to the processor when the supply voltage drops below predetermined levels. This may be done without explicit knowledge of a commanded supply voltage level for the processor.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: October 5, 2021
    Assignee: Chaoyang Semiconductor Jiangyin Technology Co., Ltd.
    Inventors: Anatoly Gelman, Taner Dosluoglu
  • Patent number: 11139811
    Abstract: A drive circuit for airbag systems, for instance includes a differential transconductance amplifier having a first input node, a second input node, an output node coupled to the second input node via a feedback line; a transistor coupled between a drive node and a supply node configured to be coupled to a power supply source; a control node coupled to the control electrode of the transistor and the output node; a Zener diode arrangement having cathode and anode terminals coupled to the supply node and the first input node, respectively; a pull-up component arranged in parallel with the Zener diode arrangement; and an enable switch coupled to the first input node and referred to ground and switchable between a conductive state and a non-conductive state with the differential transconductance amplifier providing controlled current discharging/charging of the control node to make the transistor conductive/non-conductive, respectively.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: October 5, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giancarlo Ragone, Vanni Poletto
  • Patent number: 11133742
    Abstract: A current control circuit can include: a current detection circuit configured to obtain a current detection signal for characterizing an output current of a switched capacitor converter, where the switched capacitor converter includes a plurality of first switch groups coupled between an input terminal and a ground, and where each first switch group comprises two switches coupled in series; and a voltage regulation circuit configured to regulate the output current by adjusting an equivalent impedance of the switched capacitor converter in accordance with the current detection signal.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: September 28, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Wang Zhang, Chen Zhao
  • Patent number: 11126217
    Abstract: An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 21, 2021
    Assignee: RDC SEMICONDUCTOR CO., LTD.
    Inventors: Chung-Ching Tseng, Ching-Chong Chuang
  • Patent number: 11121711
    Abstract: In an embodiment, a system includes a plurality of functional circuits, a power supply circuit, and a power management circuit. The power supply circuit may generate a shared power signal coupled to each of the functional circuits, and to generate a plurality of adjustable power signals. One adjustable power signal may be coupled to a particular functional circuit of the functional circuits. The power management circuit may a request to the power supply circuit to change a voltage level of the one particular adjustable power signal from a first voltage to a second voltage. The particular functional circuit may couple a respective power node for a sub-circuit of the particular functional circuit to either of the shared power signal or the particular adjustable power signal. The particular functional circuit may also be configured to maintain an operational voltage level on the power node.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: September 14, 2021
    Assignee: Apple Inc.
    Inventors: Keith Cox, Victor Zyuban, Norman J. Rohrer
  • Patent number: 11115013
    Abstract: In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Liliana Arcidiacono, Santi Carlo Adamo
  • Patent number: 11114859
    Abstract: An apparatus for photovoltaic power generation can include: an inverter; and at least one photovoltaic optimizer, where input terminals of each photovoltaic optimizer are coupled to output terminals of a photovoltaic panel, and output terminals of each photovoltaic optimizer are coupled in series with each other between input terminals of the inverter; where a maximum power point of the photovoltaic panel is tracked in accordance with an input voltage of the inverter when the photovoltaic optimizer operates in a first mode; and the maximum power point of the photovoltaic panel is tracked in accordance with an output voltage of the photovoltaic panel when the photovoltaic optimizer operates in a second mode.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: September 7, 2021
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventors: Kaiwei Yao, Zhiyuan Shen
  • Patent number: 11108383
    Abstract: A clock phase control circuit includes a clock input gate module, first and second shift register divider modules, and a multiplexer. The clock input gate module is configured to produce, based on an oscillating input clock signal, first and second intermediate clock signals. The first shift register divider module is configured to produce at least one first phase clock signal based on the first intermediate clock signal, where the at least one first phase clock signal has a different frequency than the first intermediate clock signal. The second shift register divider module is configured to produce at least one second phase clock signal based on the second intermediate clock signal, where the at least one second phase clock signal has a different frequency than the second intermediate clock signal. The multiplexer is configured to produce an output clock signal by selecting one of the first or second phase clock signals.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: August 31, 2021
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: David D. Moser, Michael J. Frack, Mark R. Shaffer, Daniel L. Stanley
  • Patent number: 11106236
    Abstract: An electronic circuit which is a high speed CMOS logic circuit to divide the frequency of an input signal is provided. The electronic circuit comprises a ring oscillator. The ring oscillator comprises a plurality of gated inverters. At least one of the gated inverters is configured to receive an oscillating signal and a control signal at two complementary inputs. The electronic circuit is configured to be partially gated such that a divide ratio is selectable. By means of clock partial gating, open loop clock buffering and avoiding slow combinatory logic in the data path, a very high speed multi-moduli clock divider is achieved.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: August 31, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert Callaghan Taft, Vineethraj Rajappan Nair
  • Patent number: 11108386
    Abstract: Various embodiments may provide a comparator circuit arrangement. The comparator circuit arrangement may include a preamplifier having a first input configured to be coupled to a first input voltage, a second input configured to be coupled to a second input voltage, and an output configured to generate a preamplifier output signal based on the first input voltage and the second input voltage. The comparator circuit arrangement may also include a switch circuit arrangement coupled to the preamplifier, the switch circuit arrangement configured to deactivate the preamplifier upon the second input voltage exceeding the first input voltage and further configured to activate the preamplifier upon a fall of the second input voltage, and a pull-up circuit arrangement coupled to the output of the preamplifier, the pull-up circuit arrangement configured to provide a boost voltage to the preamplifier output signal for a predetermined duration upon the fall of the second input voltage.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Agency for Science, Technology and Research
    Inventors: Yoshio Nishida, Ravinder Pal Singh
  • Patent number: 11099602
    Abstract: A method includes obtaining a trigger signal directed to a component in a subset of components of an electronic circuit, and activating a clock corresponding with the subset of components of the electronic circuit for a preliminary period in response to the trigger signal. An active period is determined based on the trigger signal. The clock remains active for the active period. One of a timer or counter is initiated for the active period. A limit is defined for the one of the timer or counter. The active period is dynamically extended for a busy period after the one of the timer or counter is initiated. The clock is deactivated following the active period.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: August 24, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Razvan Peter Figuli, Cedric Lichtenau, Stefan Payer, Michael Klein
  • Patent number: 11100224
    Abstract: An interference detection device and a detection sensitivity adjusting method are provided. A signal generating circuit generates a detection signal. A delay circuit delays the detection signal to generate a plurality of delay signals with different delay time. A decision circuit selects one of the delay signals according to a first section signal for comparing with the detection signal to generate an interference detection result, where the delay signals are used for adjusting the detection sensitivity of the interference detection device.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: August 24, 2021
    Assignee: ALI CORPORATION
    Inventors: Wei-Ke Rao, Rui Yang, Hai-Hua Wen
  • Patent number: 11101662
    Abstract: A photovoltaic system with an inverter, at least one solar panel for providing electrical power, and electrical wiring for coupling electrical power from the at least one solar panel to the inverter. Also included is a transmitter for transmitting a messaging protocol along the electrical wiring, where the protocol includes a multibit wireline signal. Also included is circuitry for selectively connecting the electrical power from the at least one solar panel along the electrical wiring to the inverter in response to the messaging protocol.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: August 24, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Il Han Kim, Xiaolin Lu
  • Patent number: 11099600
    Abstract: To improve a timing error detection accuracy in a semiconductor integrated circuit provided with storage devices operating in synchronization with a clock signal. A delay part delays a data signal by two mutually-different delay times and outputs it as first and second delay signals. A holding part holds the first and second delay signals in synchronization with a timing signal for giving an instruction on a predetermined capture timing. A setup time detection part detects whether or not one of the first and second delay signals held within a setup-time detection period from a predetermined start timing to the predetermined capture timing has changed. A hold time detection part detects whether or not the other of the first and second delay signals held within a hold-time detection period from the predetermined capture timing to a predetermined end timing has changed.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: August 24, 2021
    Assignee: Sony Corporation
    Inventors: Yuya Kawaguchi, Kazuo Kumano
  • Patent number: 11095300
    Abstract: A comparator circuit includes a first transistor configured to receive a first input and a second transistor configured to receive a second input. The comparator circuit further includes a third transistor coupled to a terminal of each of the first and second transistors. The third transistor is configured to be controlled by a first control signal. A gate of a fifth transistor is coupled to a terminal of a fourth transistor at a first node and a gate of the fourth transistor is coupled to a terminal of the fifth transistor at a second node. A sixth transistor is coupled between the first and fourth transistors. A seventh transistor is coupled between the second and fifth transistors. A gate of the sixth transistor and a gate of the seventh transistor are coupled together at a fixed voltage level.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sovan Ghosh, Amal Kumar Kundu, Janakiraman Seetharaman
  • Patent number: 11095282
    Abstract: Methods, apparatus, systems and articles of manufacture are disclosed. An example apparatus includes a gate controller coupled between an input terminal and an intermediate node, the gate controller including a first transistor coupled between the input terminal and a first node; a second transistor coupled between the first node and the intermediate node; a third transistor coupled between the input terminal and the intermediate node; and a charge pump coupled to the intermediate node; a switching network coupled between the intermediate node and an output terminal, the switching network including a high-side drive (HSD) transistor having a HSD gate terminal coupled to the intermediate node, the HSD transistor coupled between an input voltage and a switch node.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Pavol Balaz
  • Patent number: 11092990
    Abstract: An apparatus including semiconductor dies in a stack. The semiconductor dies are configured to power-up in a staggered manner. Methods for powering up an electronic device include detecting a power-up event with the semiconductor dies in the stack, and responsive to the power-up event, powering up a first semiconductor die in the stack at a first time, and powering up a second semiconductor die in the stack at a second time that is different from the first time.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Trismardawi Tanadi