Abstract: The present disclosure provides an alternatingly-switched parallel circuit, an integrated power module and an integrated power package. The alternatingly-switched parallel circuit includes a first bridge arm and a second bridge arm at least partly formed in a chip containing a plurality of first cell groups and a plurality of second cell groups. The plurality of first cell groups are configured to form the first upper bridge-arm switch and the plurality of second cell groups are configured to form the second upper bridge-arm switch, or the plurality of first cell groups are configured to form the first lower bridge-arm switch and the plurality of second cell groups are configured to form the second lower bridge-arm switch. The plurality of first cell groups and the plurality of second cell groups are switched on and off alternatingly.

Abstract: Methods and systems for a discharge power supply for providing a stabilized discharge power to a Hall-effect thruster are provided. A method includes sensing, by a first sensor circuit and based on a discharge power, a voltage sense signal, sensing, by a second sensor circuit and based on the discharge power, a current sense signal, multiplying, by a multiplying circuit, the voltage sense signal and the current sense signal to generate a feedback signal, generating, by a control logic circuit and based on control signals, further control signals, generating, by an impulse generation circuit and based on the further control signals and the feedback signal, control impulses, producing, by a transistor bridge and using the control impulses and a power source, an electrical impulses, and modifying, by an output circuit, the electrical impulses to generate the stabilized discharge power.

Abstract: The charge pump is provided, which comprises a power supply circuit and a frequency control circuit. The power supply circuit comprises at least one electric energy storage element, and charges the at least one electric energy storage element for producing a supply voltage. The frequency control circuit is coupled to the at least one electric energy storage element, and outputs an operating signal to the power supply circuit. The frequency control circuit adjusts, an operating frequency of the operating signal in according to the electricity stored in the at least one electric energy storage element for controlling charging of the at least one electric energy storage element to increase the electricity of the at least one electric energy storage element.

Abstract: A phase-locked loop circuit comprises an oscillator having a plurality of operating curves and being suitable for generating an output signal. In a calibration state the oscillator is trimmed to an operating curve for use in a normal operation state. The phase-locked loop circuit further comprises a phase/frequency detector being suitable for generating at least one error signal based on an input signal and a feedback signal generated on the basis of the output signal. The phase-locked loop circuit further comprises a loop filter being suitable for generating a loop-filter signal based on the at least one error signal, the loop-filter signal being applied to the oscillator in the normal operation state. The phase-locked loop circuit further comprises a calibration circuit being suitable for trimming the oscillator to the operating curve for use in the normal operation state on the basis of the at least one error signal.

Abstract: A delay circuit, a clock control circuit and a control method are disclosed. The delay circuit includes N-stage delay units coupled in a chain, the delay unit of each stage comprises the four-state gate circuit and an inverter circuit, an input terminal of a four-state gate circuit and an input terminal of an inverter circuit of each stage are coupled together, another input terminal of the inverter circuit is coupled to an output terminal of the inverter circuit of the next stage; an input signal is coupled to the input terminal of the four-state gate circuit and the inverter circuit of the first stage, and is output with a certain delay of time by sequentially passing through the four-state gate circuit and the inverter circuit of each stage.

Abstract: Certain aspects of the present disclosure generally relate to a sampling circuit, such as a sampling circuit for a low-voltage differential signaling (LVDS) serializer/deserializer (SerDes) system. One example sampling circuit generally includes a latching circuit and a plurality of pass-gate transistors. The latching circuit includes differential inputs, differential outputs, a clocked input circuit coupled to the differential inputs, a first cross-coupled circuit coupled to the clocked input circuit, and a second cross-coupled circuit coupled to the first cross-coupled circuit, wherein the first and second cross-coupled circuits are coupled to the differential outputs of the latching circuit. Each pass-gate transistor is coupled between one of the differential inputs of the latching circuit and a corresponding differential input of the sampling circuit.

Abstract: A delay locked loop includes a main delay circuit including a plurality of unit delay lines that generate a plurality of internal clocks by delaying an input clock, delay amounts of the plurality of unit delay lines being adjusted in response to code signals; a sub-delay circuit including a plurality of sub-delay lines that generate a plurality of phase clocks by respectively delaying the input clock and the plurality of internal clocks; a phase detector configured to compare phases of the plurality of phase clocks and provide a phase detection signal according to a result of the comparison; and a digital circuit configured to update the code signals corresponding to the plurality of unit delay lines one by one at a time when the phase detection signal is provided to the digital circuit.

Abstract: Disclosed is an electromagnetic-inductive power supply apparatus, which switches so that a plurality of coils winding around a current transformer core is connected in series to a rectification unit based on the voltage induced in the current transformer, thereby producing the power within the set range even in a state where the voltage outside the reference is induced. The disclosed electromagnetic-inductive power supply apparatus senses the voltage induced in the current transformer and switches the plurality of unit coils is connected to the rectification unit based on the voltage sensed.

Abstract: A duty cycle adjustment system includes a time-to-digital converter to generate a plurality of time-to-digital codes from an input signal, a duty cycle index generator to compute a duty cycle of the input signal based upon the plurality of time-to-digital codes, and assign a duty cycle index based upon the computed duty cycle, an input phase assignment generator to generate a first output and a second output based upon the duty cycle index, a first delay line to delay the first output to generate a third output, and a duty cycle generator to adjust the duty cycle of the input signal based upon the third output and the second output.

Abstract: An electrical machine includes as part of its stator XRAM windings for multiplying current output of the machine. The XRAM windings are coupled to switching elements that are configured to produce current multiplication for output to an external load. The XRAM windings may be in slots in the stator, or may be elsewhere in the stator, operatively coupled to other windings in the stator. The stator may be operatively coupled to a rotor and hence to an inertial energy source, such as a flywheel on the same shaft as the elements of the electrical machine. Short circuiting of select windings of the machine can advantageously cause a shifting and concentration of a machine airgap flux of the machine over other windings, and increasing their magnetic storage energy.

Abstract: A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

Abstract: A semiconductor device and a method for controlling amplitude of signal in the semiconductor device are provided. The semiconductor device comprises a signal generator configured to output a sinewave, a comparator configured to compare a magnitude of the sinewave with a magnitude of a reference signal at a first timing corresponding to a timing control signal and to output a comparison result, and a control signal adjustor configured to adjust one of the current control signal and a timing control signal depending on the comparison result of the comparator.

Abstract: A slew-limited output driver circuit facilitates finding a circuitry that allows a flexible setting of the slew-rate of an integrated circuit, with only a small footprint and latency, and which allows realizing different driver modes without additional components integrated protection against ESD. A short circuit will be solved by a slew-limited output driver circuit comprising a switchable current mirror providing an output current equal to an input current, wherein the current mirror is controlled by an additional switch, which is switched in response to control signals and/or an output current level of the output driver circuit, wherein adjustable operating modes of the slew-limited output driver circuit are realized by the control signals.

Abstract: Disclosed is a semiconductor device including a substrate with first and second regions adjacent to each other in a first direction, and first to third gate electrodes extending from the first region toward the second region. Each of the first and second regions includes a PMOSFET region and an NMOSFET region. The first to third gate electrodes extend in the first direction and are sequentially arranged in a second direction different from the first direction. The first and third gate electrodes are supplied with a first signal. The second gate electrode is supplied with a second signal that is an inverted signal of the first signal. The first gate electrode includes a first gate of the first region and a first gate of the second region. The first gates are aligned and connected with each other in the first direction.

Abstract: The present invention provides a driving circuit of a switching transistor, the driving circuit capable of suppressing an output voltage from changing sharply. A driver circuit includes a first transistor to a fourth transistor and a pre-driver. The pre-driver (i) provides a first gate signal having a negative edge slope smaller than a positive edge slope to the gate of the first transistor, (ii) provides a second gate signal having a positive edge slope smaller than a negative edge slope to the gate of the second transistor, (iii) provides a third gate signal having a positive edge slope smaller than the positive edge slope of the first gate signal to the gate of the third transistor, and (iv) provides a fourth gate signal having a negative edge slope smaller than the negative edge slope of the second gate signal to the gate of the fourth transistor.

Abstract: Aspects of the present disclosure are directed toward designs and methods of improving driving of switching devices. One proposed solution to improving driving of switching devices is an auxiliary control circuit that selectively guides the switching device through at least one switching region, permitting an improved operation of the switching device.

Abstract: This disclosure relates to a filter circuit for an output stage of an electronic circuit. The filter circuit includes a capacitor connected between a supply voltage and a first transistor. The first transistor is arranged as a diode connected transistor; a second transistor is connected to the first transistor so that the first and second transistors are arranged as a current mirror. The capacitor is connected to the first and second transistors and configured and arranged so that during operation the first transistor, the second transistor and the capacitor operate as a high pass filter.

Abstract: A voltage detector includes a voltage division circuit which outputs a divided voltage based on an input voltage, a comparison circuit which compares the divided voltage and a reference voltage to output a detection signal and a release signal, and a voltage limiting circuit which limits the divided voltage to a preset voltage.

Abstract: An electronic device includes a resistance element coupled between a supply terminal of a first voltage and an output terminal of an output signal, a driving element coupled between the output terminal of the output signal and a supply terminal of a second voltage, and suitable for operating based on a control signal, and a controller suitable for generating the control signal based on an input signal of the controller to the driving element. The controller drives an output terminal of the control signal with a first driving force during an initial period of a first transition period of the control signal, and drives the output terminal of the control signal with a second driving force different from the first driving force during the remaining period of the first transition period. The initial period is determined depending on a threshold voltage of the driving element.

Abstract: A current drive circuit has a first transistor that outputs a current, a second transistor connected to the first transistor by cascode connection, a third transistor connected to the second transistor by cascode connection, a first current source that supplies a current to the third transistor and the second transistor, a fourth transistor that shares a gate with the third transistor, a fifth transistor that is connected to the fourth transistor by cascode connection and shares a gate with the second transistor, a second current source that supplies a current to the fourth transistor and the fifth transistor, a sixth transistor that shares a gate with the third transistor and the fourth transistor and controls a gate voltage of the first transistor, and a third current source that supplies a drain current of the sixth transistor.