Patents Examined by S M Sohel Imtiaz
  • Patent number: 11978793
    Abstract: Provided is a semiconductor device in which a snubber-circuit is incorporated and can realize downsizing of a power conversion circuit into which the semiconductor device is assembled, and is flexibly applicable to various electric equipment. A semiconductor device includes a semiconductor substrate, a source electrode, a drain electrode, a plurality of trenches, a plurality of first electrodes disposed in a plurality of trenches by way of gate insulation films formed on side walls of the plurality of respective trenches, a plurality of second electrodes disposed above the plurality of first electrodes in a state where the second electrodes are spaced apart from the first electrodes, a plurality of first insulation regions, and a plurality of second insulation regions. The trenches, the first electrodes and the second electrodes are formed in stripes as viewed in a plan view. At least one of the plurality of second electrodes is connected to the drain electrode.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: May 7, 2024
    Assignee: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.
    Inventor: Kinya Ohtani
  • Patent number: 11968863
    Abstract: A display panel is provided. The display panel includes a display region, a functional layer, a first insulating film, and a first conductive film; the display region includes a pixel; the pixel includes a display element and a pixel circuit; the display element includes a first electrode and a second electrode; the second electrode includes a first opening portion; the functional layer includes the pixel circuit, a second opening portion, and an auxiliary wiring; the pixel circuit is electrically connected to the display element in the second opening portion; the auxiliary wiring includes a region overlapping with the first opening portion; the first insulating film includes a third opening portion; the third opening portion includes a region overlapping with the first opening portion; and the first conductive film is electrically connected to the second electrode and the auxiliary wiring in the third opening portion.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Masataka Nakada, Tomoya Aoyama
  • Patent number: 11968852
    Abstract: A light-emitting device includes: a first electrode and a second electrode that are superposed; an emitting layer (EML) located between the first electrode and the second electrode; and an electron transport layer (ETL) located between the first electrode and the EML. The ETL includes a first surface proximate to the EML and a second surface proximate to the first electrode, oxygen vacancies is formed in the ETL, and a concentration of oxygen vacancies in the ETL gradually increases from the second surface to the first surface.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: April 23, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wenhai Mei, Yichi Zhang
  • Patent number: 11963430
    Abstract: An object is to provide a highly reliable display unit having a function of sensing light. The display unit includes a light-receiving device and a light-emitting device. The light-receiving device includes an active layer between a pair of electrodes. The light-emitting device includes a hole-injection layer, a light-emitting layer, and an electron-transport layer between a pair of electrodes. The light-receiving device and the light-emitting device share one of the electrodes, and may further share another common layer between the pair of electrodes. The hole-injection layer is in contact with an anode and contains a first compound and a second compound. The electron-transport property of the electron-transport layer is low; hence, the light-emitting layer is less likely to have excess electrons. Here, the first compound is the material having a property of accepting electrons from the second compound.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taisuke Kamada, Ryo Hatsumi, Daisuke Kubota, Naoaki Hashimoto, Tsunenori Suzuki, Harue Osaka, Satoshi Seo
  • Patent number: 11957005
    Abstract: A display device includes: a substrate; scan lines extending in a first direction, and arranged along a second direction crossing the first direction on the substrate; data lines extending in the second direction, and arranged along the first direction on the substrate; a display area including pixels connected to the scan lines and the data lines; and a non-display area around the display area, and including compensation capacitors connected to some scan lines from among the scan lines. A sum of a capacitance of q odd scan lines or q even scan lines that are adjacent to each other from among the scan lines increases in the second direction, where q is a positive integer.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 9, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Seo Won Choe, Ki Wook Kim, Yang Wan Kim, Hyun Woong Kim, Eun Byul Jo
  • Patent number: 11955589
    Abstract: A light-emitting device comprises a carrier, which comprises a plurality of side surfaces, an insulating layer, an upper conductive layer arranged on the insulating layer, a lower conductive layer arranged under the insulating layer, and a plurality of conductive through holes arranged between and connected to the upper conductive layer and the lower conductive layer; a plurality of light-emitting units arranged on and electrically connected to the upper conductive layer; and a transparent unit fully covering the plurality of light-emitting units, and exposing the lower conductive layer, wherein the plurality of conductive through holes are not completely buried within the insulating layer, and each conductive through hole is sandwiched by two adjacent ones of the plurality of side surfaces.
    Type: Grant
    Filed: July 15, 2021
    Date of Patent: April 9, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Min-Hsun Hsieh, Tzu-Hsiang Wang
  • Patent number: 11956950
    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.
    Type: Grant
    Filed: December 13, 2022
    Date of Patent: April 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: John D. Hopkins, Nancy M. Lomeli
  • Patent number: 11949005
    Abstract: Provided is a semiconductor device that includes a first conductivity type well region below a gate runner portion, wherein a diode region includes first contact portions, a first conductivity type anode region, and a second conductivity type cathode region; wherein the well region contacts the diode region in the first direction, and when an end of the well region, an end of at least one of first contact portions, and an end of the cathode region that face one another in the first direction are imaginary projected on an upper surface of the semiconductor substrate, a first distance is longer than a second distance, the first distance being a distance between the end of the well region and the end of the cathode region, and the second distance being a distance between the end of the well region and the end of the at least one first contact portion.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: April 2, 2024
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Misaki Takahashi, Yuichi Harada, Kouta Yokoyama
  • Patent number: 11936231
    Abstract: Systems and methods for detecting electrical connection and disconnection on an USB Type-A charging port like power adapters, power banks and car chargers having one or more USB Type-A charging port of an USB device. The system includes: a voltage source; a MOSFET SWITCH gate driver, in USB type-A connected state, that operatively couples MOSFET SWITCH with voltage source and VBUS supply of USB type-A port; charge pump; a current sense differential amplifier; and a control unit configured to: monitor VBUS current, and detect potential disconnected state of connected USB type-A port; and monitor VBUS voltage and compare VBUS voltage with predetermined voltage to sense external condition such that VBUS voltage drops because of load capacitance and load current. The control unit is further configured to, when the duty cycle has reached a minimum VBUS current, detect the USB type-A disconnection with a charge pump state.
    Type: Grant
    Filed: December 12, 2022
    Date of Patent: March 19, 2024
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Rakesh Kumar Polasa, Satish Anand Verkila, Burle Naga Satyanarayana
  • Patent number: 11936342
    Abstract: A semiconductor device package includes a plurality of input leads and an output lead, a plurality of transistor amplifier dies having inputs respectively coupled to the plurality of input leads, and a combination circuit configured to combine output signals received from the plurality of transistor amplifier dies and output a combined signal to the output lead.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: March 19, 2024
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventors: Marvin Marbell, Jonathan Chang, Haedong Jang, Qianli Mu, Michael LeFevre, Jeremy Fisher, Basim Noori
  • Patent number: 11935884
    Abstract: Overvoltage protection circuits are provided. In some embodiments, an overvoltage protection circuit includes a first diode made of a first semiconductor material having a bandgap width greater than that of silicon. A second diode is included and is electrically cross-coupled with the first diode. The second diode is made of a second semiconductor material different from the first semiconductor material.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: March 19, 2024
    Assignees: STMICROELECTRONICS S.r.l., STMICROELECTRONICS (TOURS) SAS
    Inventors: Jean-Michel Simonnet, Sophie Ngo, Simone Rascuna'
  • Patent number: 11929427
    Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: March 12, 2024
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Chao-Hsing Huang, Yu-Chung Chin, Kai-Yu Chen
  • Patent number: 11929337
    Abstract: A microelectronic assembly comprises a microelectronic element, a redistribution structure, a plurality of backside conductive components and an encapsulant. The redistribution structure may be configured to conductively connect bond pads of the microelectronic element with terminals of the microelectronic assembly. The plurality of back side conductive components may be etched monolithic structures and further comprise a back side routing layer and an interconnection element integrally formed with the back side routing layer and extending in a direction away from the back side routing layer. The back side routing layer of at least one of the plurality of back side conductive components overlies the rear surface of the microelectronic element. An encapsulant may be disposed between each interconnection element. The back side routing layer of the at least one of the plurality of back side conductive components extends along one of the opposed interconnection surfaces.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: March 12, 2024
    Assignee: Invensas LLC
    Inventors: Chok J. Chia, Qwai H. Low, Patrick Variot
  • Patent number: 11925085
    Abstract: A display device includes a display panel including a plurality of pixels, a first panel pad, and a second panel pad and a circuit board including a first substrate pad and a second substrate pad to apply a first power voltage to the first panel pad and the second panel. The display panel further includes a first power line pattern connected to the second substrate pad to apply the first power voltage to the pixels and a second power line pattern connected to the first substrate pad. The circuit board includes a first electrostatic discharge protection circuit connected between the first substrate pad and the second substrate pad, a substrate power pattern electrically connected to the first substrate pad, a ground pattern receiving a ground voltage, and a second electrostatic discharge protection circuit connected between the substrate power pattern and the ground pattern.
    Type: Grant
    Filed: February 6, 2023
    Date of Patent: March 5, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventor: Moon-Chul Park
  • Patent number: 11925097
    Abstract: An object is to provide a highly reliable display unit having a function of sensing light. The display unit includes a light-receiving device and a light-emitting device. The light-receiving device includes an active layer between a pair of electrodes. The light-emitting device includes a hole-injection layer, a light-emitting layer, and an electron-transport layer between a pair of electrodes. The light-receiving device and the light-emitting device share one of the electrodes, and may further share another common layer between the pair of electrodes. The hole-injection layer is in contact with an anode and contains a first compound and a second compound. The electron-transport property of the electron-transport layer is low; hence, the light-emitting layer is less likely to have excess electrons. Here, the first compound is the material having a property of accepting electrons from the second compound.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: March 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taisuke Kamada, Ryo Hatsumi, Daisuke Kubota, Naoaki Hashimoto, Tsunenori Suzuki, Harue Osaka, Satoshi Seo
  • Patent number: 11916040
    Abstract: The present invention discloses a bonding cavity structure and a bonding method, the bonding cavity structure comprises an upper carrier and a lower carrier, a gas-flow forming mechanism, which comprises multiple open-close integrated arms, the integrated arms are provided with multiple nozzles facing to wafer bonding surfaces, and the nozzles are switched to gas nozzles or vacuum suction nozzles, a closed space is formed by all the integrated arms closed together with the carriers, all the nozzle located on a side of two wafers are set as the gas nozzles, which blow gas parallel to the wafer bonding surfaces, meanwhile, all the nozzles located on the other side of the two wafers are set as the vacuum suction nozzles, which suck the gas blown from the gas nozzle at corresponding position, a high-speed gas-flow is generated between the two wafers, so as to produce a low pressure of Bernoulli effect, the wafers are not only subjected to thrust forces from backsides, but tension forces between the bonding surfac
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: February 27, 2024
    Assignees: Shanghai IC R&D Center Co., Ltd., Shanghai Integrated Circuit Equipment & Materials Industry Innovation Center Co., Ltd
    Inventor: Xinyu Li
  • Patent number: 11916064
    Abstract: An integrated circuit with a fault reporting structure. The integrated circuit has at least one power MOSFET having a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, and the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells. The fault reporting structure has a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: February 27, 2024
    Assignee: Monolithic Power Systems, Inc.
    Inventors: Chiahsin Chang, Tao Zhao, Xintong Lyu
  • Patent number: 11908538
    Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: February 20, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Wei Peng, Jiann-Tyng Tzeng, Kam-Tou Sio
  • Patent number: 11908886
    Abstract: A power converter is embodied on a semiconductor substrate member and has a first region with a passive electrical component with a first electrically conductive layer pattern of an electrically conductive material and a second electrically conductive layer pattern of an electrically conductive material deposited on respective sides of the semiconductor substrate member. A trench or through-hole is formed (by etching) in the substrate within the first region, and the electrically conductive material is deposited at least on a bottom portion of the trench or on a sidewall of the through-hole and electrically connected to one or both of the first conductive layer pattern and the second conductive layer pattern. A second region has an active semiconductor component integrated with the semiconductor substrate by being fabricated by a semiconductor fabrication process. There is also provided a power supply, such as a DC-DC converter, embedded the semiconductor substrate member.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: February 20, 2024
    Assignee: Danmarks Tekniske Universitet
    Inventors: A. A. Nour Yasser, Hoa Le Thanh
  • Patent number: 11910681
    Abstract: A display apparatus includes a substrate, a first-layer power supply line disposed on a substrate in a peripheral area which surrounds a display area in which an image is displayed, a first insulation layer on the substrate on which the first-layer power supply line is disposed, a second-layer power supply line disposed on the first insulation layer and the first-layer power supply line, and contacting the first-layer power supply line, a second insulation layer on the first insulation layer on which the second-layer power supply line is disposed, and a light emitting structure disposed on the second insulation layer and including a first electrode, a light emitting layer and a second electrode which is electrically connected to the second-layer power supply line.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yoonsun Choi, Seong Ryong Lee