Abstract: The present invention discloses a bonding cavity structure and a bonding method, the bonding cavity structure comprises an upper carrier and a lower carrier, a gas-flow forming mechanism, which comprises multiple open-close integrated arms, the integrated arms are provided with multiple nozzles facing to wafer bonding surfaces, and the nozzles are switched to gas nozzles or vacuum suction nozzles, a closed space is formed by all the integrated arms closed together with the carriers, all the nozzle located on a side of two wafers are set as the gas nozzles, which blow gas parallel to the wafer bonding surfaces, meanwhile, all the nozzles located on the other side of the two wafers are set as the vacuum suction nozzles, which suck the gas blown from the gas nozzle at corresponding position, a high-speed gas-flow is generated between the two wafers, so as to produce a low pressure of Bernoulli effect, the wafers are not only subjected to thrust forces from backsides, but tension forces between the bonding surfac

Abstract: An integrated circuit with a fault reporting structure. The integrated circuit has at least one power MOSFET having a plurality of MOSFET cells with each MOSFET cell having a drain metal and a source metal, and the integrated circuit has a power MOSFET area for routing the drain metals and the source metals of the plurality of MOSFET cells. The fault reporting structure has a metal net routed in the power MOSFET area or in an area above or below the power MOSFET area.

Abstract: Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.

Abstract: A power converter is embodied on a semiconductor substrate member and has a first region with a passive electrical component with a first electrically conductive layer pattern of an electrically conductive material and a second electrically conductive layer pattern of an electrically conductive material deposited on respective sides of the semiconductor substrate member. A trench or through-hole is formed (by etching) in the substrate within the first region, and the electrically conductive material is deposited at least on a bottom portion of the trench or on a sidewall of the through-hole and electrically connected to one or both of the first conductive layer pattern and the second conductive layer pattern. A second region has an active semiconductor component integrated with the semiconductor substrate by being fabricated by a semiconductor fabrication process. There is also provided a power supply, such as a DC-DC converter, embedded the semiconductor substrate member.

Abstract: A display apparatus includes a substrate, a first-layer power supply line disposed on a substrate in a peripheral area which surrounds a display area in which an image is displayed, a first insulation layer on the substrate on which the first-layer power supply line is disposed, a second-layer power supply line disposed on the first insulation layer and the first-layer power supply line, and contacting the first-layer power supply line, a second insulation layer on the first insulation layer on which the second-layer power supply line is disposed, and a light emitting structure disposed on the second insulation layer and including a first electrode, a light emitting layer and a second electrode which is electrically connected to the second-layer power supply line.

Abstract: A display device of the invention includes pixels each connected to at least one of scan lines and at least one of emission lines, a scan driver providing scan signals to the scan lines, and an emission driver including stages connected to the emission lines, each of the stages providing an emission signal to a corresponding emission line. A first stage among the stages includes a first transistor including a first electrode connected to a first power source line, a second electrode connected to a first emission line, and a gate electrode connected to a first scan line, and a second transistor including a first electrode connected to a first node and a second electrode connected to the first emission line.

Abstract: A CMOS image sensor (CIS) package includes a package substrate, a CIS chip arranged on an upper surface of the package substrate and electrically connected with the package substrate, a glass arranged over the CIS chip, and an adhesive layer interposed between an edge portion of an upper surface of the CIS chip and an edge portion of a lower surface of the glass to attach the glass to the CIS chip. An interlocking recess is provided to at least one of the CIS chip and the glass, and the adhesive layer comprises an interlocking protrusion inserted into the interlocking recess.

Abstract: An organic light emitting element includes a first electrode, a hole transport region disposed on the first electrode, an emission layer disposed on the hole transport region, an electron transport region disposed on the emission layer and including an electron transport layer, and a second electrode disposed on the electron transport region. The hole transport region may include a first hole transport layer having a first refractive index, a second hole transport layer disposed on the first hole transport layer and having a second refractive index less than the first refractive index, and a third hole transport layer disposed below the first hole transport layer and having a third refractive index less than the first refractive index. A difference between the first refractive index and the second refractive index, and a difference between the first refractive index and the third refractive index may each be about 0.1 to about 1.0.

Abstract: Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.

Abstract: A voltage output circuit and an electronic cigarette are provided. The voltage output circuit includes a control chip and a step-down switch chip. When a first switch element turns on, the modulation signal output terminal of the control chip outputs a pulse modulation signal to a first control terminal of the step-down switch chip, and access between a first access terminal and a second access terminal of the step-down switch chip is established, based on the effective pulse modulation signal. The output voltage of the second access terminal is less than a system power voltage. The voltage output circuit and the electronic cigarette outputs the pulse modulation signal to the step-down switch chip by the control chip, and the step-down switch chip outputs a suitable driving voltage to the load, such as a thermal wire, the voltage output circuit with simplified structure is adjustable and improved.

Abstract: A method for manufacturing a detection device, the detection device comprising a substrate, a plurality of sensor elements arranged on a first principal surface of the substrate, and an insulating film provided above the substrate so as to cover the sensor elements, and the method comprising: causing the first principal surfaces of a pair of the substrates on each of which the sensor elements, the insulating film, and a first projection projecting from a surface of the insulating film are formed to face each other, and bonding together the pair of the substrates; and polishing a second principal surface of each of the pair of the substrates on a side opposite to the first principal surface in a state where the pair of the substrates are bonded together.

Abstract: Integrated circuits described herein implement multiplexer (MUX) gate system. An integrated circuit includes a plurality of inputs coupled with a first stage of the integrated circuit. The first stage includes a plurality of first Schottky diodes and a plurality of N-type transistors. Each input is coupled with a respective first Schottky diode and N-type transistor. The integrated circuit also includes a plurality of outputs of the first stage coupled with a second stage of the integrated circuit. The second stage includes a plurality of second Schottky diodes and a plurality of P-type transistors. Each output coupled with a respective second Schottky diode and P-type transistor. The integrated circuit further includes a plurality of outputs of the second stage coupled with a set of transistors including a P-type transistor and an N-type transistor, and an output of the set of transistors coupled with an output of the MUX gate system.

Abstract: A light-emitting structure includes a substrate, a sub-pixel stack over a surface of the substrate, and a bank including a first bank portion and a second bank portion. The sub-pixel stack has an emissive stack including an emissive layer between a first transport layer and a second transport layer, a first electrode layer coupled to the first transport layer, and a second electrode layer coupled to the second transport layer. The second bank portion is between the first bank portion and the sub-pixel stack, and the bank surrounding at least the emissive stack and the first electrode layer forms an interior space above the sub-pixel stack.

Abstract: A display substrate has at least one display region and at least one non-display region, and a non-display region is located at at least one side of a display region. The display substrate includes a base, a plurality of light-emitting devices, and an encapsulation layer. The plurality of light-emitting devices are located in the at least one display region and disposed on a side of the base. The encapsulation layer is disposed on a side of the plurality of light-emitting devices facing away from the base, and configured to encapsulate the plurality of light-emitting devices. A surface, proximate to the base, of a portion of the encapsulation layer located in the non-display region is unevenly arranged.

Abstract: A display device includes: a first pixel region, a second pixel region, and a third pixel region that are adjacent to each other in a plan view; a display panel including a first light emitting element overlapping with the first pixel region, a second light emitting element overlapping with the second pixel region, and a third light emitting element overlapping with the third pixel region; and a refractive index control layer including a first refractive index control part corresponding to the first light emitting element, and a second refractive index control part corresponding to the second light emitting element. The first refractive index control part and the second refractive index control part have different refractive indices from each other.

Abstract: A power electronics converter includes a multi-layer planar carrier substrate having a plurality of electrically conductive layers, at least one electrical connection, and a converter commutation cell comprising a power circuit and a gate driver circuit. The power circuit includes at least one power semiconductor switching element and at least one capacitor. Each power semiconductor switching element is included in a power semiconductor prepackage having one or more power semiconductor switching elements embedded in a solid insulating material. The power electronics converter includes a heat sink configured to remove heat from the power semiconductor prepackage. A converter parameter ? is greater than or 20 equal to 100 kW/m3K, ? being defined as a heat transfer coefficient between the heat removal side of the power semiconductor prepackage and a cooling medium of the heat sink divided by the size of a gap between the power semiconductor prepackage and the heat sink.

Abstract: A top emitting quantum dot light emitting diode (QLED) apparatus for an emissive display apparatus sub-pixel, with at least one bank defining an emissive region of the emissive display apparatus sub-pixel, includes an emissive layer deposited in the emissive region between a first electrode and a second electrode. The first electrode includes a reflective metal, and the second electrode has a transparent conductive electrode and an auxiliary electrode. The bank has a sloped portion adjacent the emissive region. The auxiliary electrode includes a reflective conductive metal and is configured to cover the sloped portion, and the sloped portion is configured at an angle, such that the auxiliary electrode reflects internally reflected light out of the sub-pixel in a viewing direction, and the auxiliary electrode is configured with a partially light scattering surface to broaden a reflective angle range of the auxiliary electrode.

Abstract: The present disclosure relates to a new combiner/attenuator circuit that provides improved performance, specifically the combiner/attenuator circuit disclosed is capable of operating at a temperature of 4K and provides an improved frequency response and filtering.

Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip, the method includes depositing a grid layer over a substrate. The grid layer is patterned to form a grid structure. The grid structure comprises a plurality of sidewalls defining a plurality of openings. A ferroelectric layer is deposited over the substrate. The ferroelectric layer fills the plurality of openings and is disposed along the plurality of sidewalls of the grid structure. An upper conductive structure is formed over the grid structure.

Abstract: A connection structure of a snubber circuit within a semiconductor device includes: a first substrate having a first electrode wiring line; a second substrate facing the first substrate, the second substrate having a second electrode wiring line facing the first electrode wiring line; and a stack ceramic capacitor having connection terminals provided on opposite ends, respectively, of the stack ceramic capacitor installed in an upright position in such a manner that entire surfaces of the connection terminals are connected to the first and second electrode wiring lines, respectively, where the stack ceramic capacitor is installed adjacent to a switching element attached on the first substrate, and the connection terminal and one electrode terminal on the switching element are connected with the first electrode wiring line interposed therebetween.