Patents Examined by S M Sohel Imtiaz
  • Patent number: 11689041
    Abstract: Systems and methods for detecting electrical connection and disconnection on an USB Type-A charging port like power adapters, power banks and car chargers having one or more USB Type-A charging port of an USB device. The system includes: a voltage source; a MOSFET SWITCH gate driver, in USB type-A connected state, that operatively couples MOSFET SWITCH with voltage source and VBUS supply of USB type-A port; charge pump; a current sense differential amplifier; and a control unit configured to: monitor VBUS current, and detect potential disconnected state of connected USB type-A port; and monitor VBUS voltage and compare VBUS voltage with predetermined voltage to sense external condition such that VBUS voltage drops because of load capacitance and load current. The control unit is further configured to, when the duty cycle has reached a minimum VBUS current, detect the USB type-A disconnection with a charge pump state.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 27, 2023
    Assignee: SiliConch Systems Pvt Ltd
    Inventors: Rakesh Kumar Polasa, Satish Anand Verkila, Burle Naga Satyanarayana
  • Patent number: 11688777
    Abstract: In an embodiment, a semiconductor device is provided that includes a lateral transistor device having a source, a drain and a gate, and a monolithically integrated capacitor coupled between the gate and the drain.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: June 27, 2023
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Eric G. Persson, Reenu Garg
  • Patent number: 11688723
    Abstract: An electrical vertical take-off and landing (eVTOL) aircraft includes a plurality of electrical propulsion units (EPUs), each EPU having a propeller or a fan configured to be driven to rotate by an electrical motor arranged to receive electrical power from a respective power electronics converter. Each power electronics converter includes a converter commutation cell having a power circuit and a gate driver circuit, the power circuit including at least one power semiconductor switching element and at least one capacitor. At least one terminal of each power conducting switching element is connected to at least one electrically conductive layer of a multi-layer planar carrier substrate at an electrical connection side of a power semiconductor prepackage, which includes at least one electrically conductive layer located on an opposite side of the power semiconductor switching element to the electrical connection side of the power semiconductor prepackage.
    Type: Grant
    Filed: August 31, 2022
    Date of Patent: June 27, 2023
    Assignee: Rolls-Royce Deutschland Ltd & Co KG
    Inventors: Uwe Waltrich, Stanley Buchert
  • Patent number: 11688815
    Abstract: A cover for an electronic package is manufactured by placing an optical insert, having opposite faces and configured to allow light radiation to pass therethrough, between two opposite faces of a cavity of a mold in a position such that said optical faces of the optical insert make contact with said opposite faces of the cavity of the mold. A coating material is injected into the cavity and around the optical insert. The coating material is set to obtain a substrate that is overmolded around the optical insert so as to produce the cover. An electronic package includes an electronic chip mounted to a support substrate with the cover formed by the overmolded substrate mounted to the support substrate.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 27, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Alexandre Mas, Eric Saugier, Gaetan Lobascio, Benoit Besancon
  • Patent number: 11670688
    Abstract: The disclosure provides a semiconductor apparatus capable of keeping a semiconductor characteristics and realizing excellent semiconductor properties even when using an n type semiconductor (gallium oxide, for example) having a low loss at a high voltage and having much higher dielectric breakdown electric field strength than SiC. A semiconductor apparatus includes a gate electrode and a channel layer formed of a channel directly or through other layers on a side wall of the gate electrode, and wherein a portion of or whole the channel layer may be a p type oxide semiconductor (iridium oxide, for example).
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: June 6, 2023
    Assignee: FLOSFIA INC.
    Inventors: Tokiyoshi Matsuda, Masahiro Sugimoto, Takashi Shinohe
  • Patent number: 11659758
    Abstract: An object is to provide a highly reliable display unit having a function of sensing light. The display unit includes a light-receiving device and a light-emitting device. The light-receiving device includes an active layer between a pair of electrodes. The light-emitting device includes a hole-injection layer, a light-emitting layer, and an electron-transport layer between a pair of electrodes. The light-receiving device and the light-emitting device share one of the electrodes, and may further share another common layer between the pair of electrodes. The hole-injection layer is in contact with an anode and contains a first compound and a second compound. The electron-transport property of the electron-transport layer is low; hence, the light-emitting layer is less likely to have excess electrons. Here, the first compound is the material having a property of accepting electrons from the second compound.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 23, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Taisuke Kamada, Ryo Hatsumi, Daisuke Kubota, Naoaki Hashimoto, Tsunenori Suzuki, Harue Osaka, Satoshi Seo
  • Patent number: 11651884
    Abstract: Structures that include a peaking inductor and a T-coil, and methods associated with forming such structures. A back-end-of-line interconnect structure includes a first metallization level, a second metallization level, and a third metallization level arranged between the first metallization level and the second metallization level. The T-coil includes a first inductor with a first coil arranged in the first metallization level and a second inductor with a second coil arranged in the second metallization level. A peaking inductor includes a coil arranged in the third metallization level. The first coil of the first inductor, the second coil of the second inductor, and the coil of the peaking inductor are stacked in the back-end-of-line interconnect structure with an overlapping arrangement.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: May 16, 2023
    Assignee: GlobalFoundries U.S. Inc.
    Inventors: Venkata N. R. Vanukuru, Umesh Kumar Shukla, Sandeep Torgal
  • Patent number: 11653496
    Abstract: The total silicon area used by a plurality of high voltage transistors in an array of NAND cells is reduced by modifying the silicon area layout such that the size of the source and drain of each of the plurality of high voltage transistors is dependent on the maximum voltage to be applied to each of the source and drain for the respective one of the plurality of high voltage transistors.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Chang Wan Ha, Chuan Lin, Deepak Thimmegowda, Zengtao Liu, Binh N. Ngo, Soo-yong Park
  • Patent number: 11652046
    Abstract: According to one or more embodiments, a semiconductor integrated circuit device includes a first inductor portion, a second inductor portion, and a third inductor portion. The first inductor portion is in a first region of a first wiring layer. The second inductor portion is disposed in a second region of the first wiring layer. The third inductor portion is on a second wiring layer spaced from the first wiring layer in a first direction. The third inductor portion includes a first end portion electrically connected to a first end of the first inductor portion, a second end portion electrically connected to a first end of the second inductor portion, and a third end portion between the first and second end portions. The first inductor portion, the second inductor portion, and the third inductor portion constitute an inductor element.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: May 16, 2023
    Assignee: Kioxia Corporation
    Inventor: Go Urakawa
  • Patent number: 11646374
    Abstract: Embodiments herein describe techniques for a semiconductor device including a gate stack with a ferroelectric-oxide layer above a channel layer and in contact with the channel layer, and a top electrode above the ferroelectric-oxide layer. The ferroelectric-oxide layer includes a domain wall between an area under a nucleation point of the top electrode and above a separation line of the channel layer between an ON state portion and an OFF state portion of the channel layer. A resistance between a source electrode and a drain electrode is modulated in a range between a first resistance value and a second resistance value, dependent on a position of the domain wall within the ferroelectric-oxide layer, a position of the ON state portion of the channel layer, and a position of the OFF state portion of the channel layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: May 9, 2023
    Assignee: Intel Corporation
    Inventors: Ashish Verma Penumatcha, Tanay Gosavi, Uygar Avci, Ian A. Young
  • Patent number: 11647634
    Abstract: A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: May 9, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Cheng Yang, Meng-Han Lin, Han-Jong Chia, Sheng-Chen Wang, Chung-Te Lin
  • Patent number: 11646225
    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myeong-Dong Lee, Keunnam Kim, Dongryul Lee, Minseong Choi, Jimin Choi, Yong Kwan Kim, Changhyun Cho, Yoosang Hwang
  • Patent number: 11644159
    Abstract: An indicator circuit for an emergency light, including: a charging circuit, in connection with a positive terminal of a lithium battery and configured to charge the lithium battery; a battery protection circuit, in connection with a negative terminal of the lithium battery and configured to provide protection against overvoltage and overcurrent of an electrical signal output by the lithium battery; a main control circuit, in connection with the negative terminal of the lithium battery and configured to compare the electrical signal output by the lithium battery with a reference voltage signal and output a control signal; and a drive circuit, in connection with the main control circuit and an indicator light, and configured to drive the indicator light to illuminate according to the control signal and turn off the indicator light in case of abnormal conditions.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: May 9, 2023
    Assignee: XIAMEN ECO LIGHTING CO., LTD.
    Inventors: Jianxin Xie, Mingshu Xu, Tian Lan
  • Patent number: 11626449
    Abstract: In a display device, an inorganic insulating layer, a metal layer, a flattering film, a first electrode, an edge cover, a function layer, and a second electrode are formed, in that order, on a base substrate. The edge cover covers an edge of the first electrode and includes a first opening exposing the first electrode. The function layer is formed covering the first opening and an edge of the edge cover. The flattening film includes a first planar portion and a second planar portion having a film thickness smaller than that of the first planar portion, is configured to electrically connect the first electrode and the metal layer via a contact hole formed in the first planar portion, and overlaps the first opening of the edge cover at at least a portion of the second planar portion.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: April 11, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tohru Okabe, Ryosuke Gunji, Shinsuke Saida, Shinji Ichikawa, Kohji Ariga, Hiroki Taniyama, Yoshihiro Nakada, Koji Tanimura, Yoshihiro Kohara, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11621647
    Abstract: A semiconductor device is provided, comprising a plurality of circuit portions, and a first connection portion and a second connection portion that are formed of planar conductive materials and connected to any of the circuit portions, wherein the first connection portion and the second connection portion are arranged with respective main surfaces facing each other, the first connection portion and the second connection portion each comprising a circuit connection end connected to the circuit portions, a path restriction portion for restricting a current path in the main surface, directions of currents flowing through the current paths between the path restriction portions and the circuit connection ends are different in the first connection portion and the second connection portion. Directions of currents flowing through the current paths between the path restriction portions and the circuit connection ends are preferably different in the first connection portion and the second connection portion.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: April 4, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Sayaka Yamamoto
  • Patent number: 11620922
    Abstract: In a cross section of a bending section of a frame region, a first opening opening upward is formed in at least one layer of inorganic film included in a TFT layer. A first organic film is provided to plug the first opening. A frame wiring line is provided on the first organic film. A second organic film is provided to cover the frame wiring line. A second opening opening upward is formed in the first organic film on an inner side with respect to the first opening.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: April 4, 2023
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shinji Ichikawa, Tohru Okabe, Shinsuke Saida, Ryosuke Gunji, Hiroki Taniyama, Yoshihiro Nakada, Hiroharu Jinmura, Akira Inoue
  • Patent number: 11620936
    Abstract: Integrated active-matrix light emitting pixel arrays based displays and methods of fabricating the integrated displays are provided. One of the methods include: forming first color light emitting diodes (LEDs) and respective intermediate metallic layers on a first substrate, integrating the first color LEDs with pixel circuits in a backplane device, injecting laser pulses into particular first color LEDs, such that each particular first color LED is individually separated from the first substrate and locally bonded with a respective pixel circuit through a respective intermediate metallic layer, and removing the first substrate from the backplane device. The backplane device bonded with the particular first color LEDs can be further bonded with other different color LEDs formed on other substrates. Other first color LEDs without exposure of the laser pulses are removed with the first substrate and can be further used to integrate with another backplane device bonded with another color LEDs.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: April 4, 2023
    Inventor: Shaoher Pan
  • Patent number: 11615719
    Abstract: The present disclosure provides a display panel and a display device. The display panel includes: a base substrate including a display unit and a bendable unit, the bendable unit being connected to the display unit and bendable to a back of the display unit; a multiplexer on the bendable unit; and a metal shielding portion on a side of the multiplexer away from the base substrate, wherein an orthographic projection of the metal shielding portion on the base substrate covers an orthographic projection of the multiplexer on the base substrate, and the metal shielding portion is connected to a fixed voltage signal to shield signal interference caused by the multiplexer.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: March 28, 2023
    Assignees: Chengdu BOE Optoelectronics Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Mengmeng Du, Xiangdan Dong, Hongwei Ma, Jun Yan, Bo Cheng
  • Patent number: 11616453
    Abstract: An integrated circuit includes a memory array that stores data, a rectifying circuit that rectifies an alternating current and generates a direct-current voltage, and a logic circuit that reads data stored in a memory. The memory array includes a first semiconductor memory element having a first semiconductor layer. The rectifying circuit includes a second semiconductor rectifying element having a second semiconductor layer. The logic circuit includes a third semiconductor logic element having a third semiconductor layer. The second semiconductor layer is a functional layer exhibiting a rectifying action and the third semiconductor layer is a channel layer of a logic element. All the first, second and third semiconductor layers, the functional layer exhibiting a rectifying action and the channel layer are formed of the same material including at least one selected from an organic semiconductor, a carbon nanotube, graphene, or fullerene.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: March 28, 2023
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Hiroji Shimizu, Seiichiro Murase
  • Patent number: 11602177
    Abstract: A voltage output circuit and an electronic cigarette are provided. The voltage output circuit includes a control chip and a step-down switch chip. When a first switch element turns on, the modulation signal output terminal of the control chip outputs a pulse modulation signal to a first control terminal of the step-down switch chip, and access between a first access terminal and a second access terminal of the step-down switch chip is established, based on the effective pulse modulation signal. The output voltage of the second access terminal is less than a system power voltage. The voltage output circuit and the electronic cigarette outputs the pulse modulation signal to the step-down switch chip by the control chip, and the step-down switch chip outputs a suitable driving voltage to the load, such as a thermal wire, the voltage output circuit with simplified structure is adjustable and improved.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: March 14, 2023
    Assignee: Changzhou Patent Electronic Technology Co., ltd
    Inventors: Wei-Hua Qiu, Kui Liu